MSI State Diagram for a Local Cache g Three states for a cache block in a local (private)cache similar to snooping coherence protocol CPU read hit g Requests by processor validate/ Acknowledge CPU read /Read miss message ☆B| ack arrows Invalid Shared (read only) Requests by directory CPU write ☆ Red arrows E∽E Modified (read/write CPU read hit CPU write miss/ CPU write hit Write-back, Write-miss message 2021/22 计算机体系结构
MSI State Diagram for a Local Cache 2021/2/2 计算机体系结构 18
to MOSI State Diagram for Directory Read Miss request by p Read Miss request by p Get block from memory Data reply to P Data reply to P, Set presence[p]=1 Set presence[P]=1 Uncached Shared (read only Write miss request by P E9x Read Miss request by P Data reply to P, Set presence[P]=1 o%/ Write Miss(or Invalidate)request by P Invalidate all sharers, clear presence bits Modified Data reply to P, Set presence[P] =1 Owned by shared ( Processor P cache Read miss by Q, Fetch P, Data reply to Q Write mis Write-Back by P- Presence[Pl=0 Request by Q Fetch-lnvalidate P, Data-reply to Q, Presence[pl= 0, Presence [Ql=1 2021/22 计算机体系结构
MOSI State Diagram for Directory 2021/2/2 计算机体系结构 19