例1:设计3-8线译码器 LIBRARY IEEE: USE IEEESTD LOGIC 1164ALL: ENTITY ymg 83 IS 译码器设计 PORT(A, B, C: IN STD LOGIC; Y: OUTSTD LOGIC VECTOR(7 DOWNTOO)) END ymq83; 请注意 数据类型 的声明
三 译 码 器 设 计 例1：设计3－8线译码器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ymq83 IS PORT(A,B,C: IN STD_LOGIC; Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ymq83; 请注意 数据类型 的声明
例1:设计3-8线译码器 aRChitECtURE behavior oF ymg 83 IS SIGNAL INDATA: STD LOGIC VECTOR(2 DOWNTOO); BEGIN INDATA<=C&B&A 该描述 译码器设计 PROCESSOINDATA) BEGIN 不具有 CASE INDATA IS 优先级 WHEN“000”→>Y<=“11110”; wIEN“001”=>Y<=“11111101 WHEN“010”=>Y<=“1ll1011”; WHEN“011”→Y<=“1111011”; WFEN“100”=>Y<=“1110lll”; WHEN“101”→>Y<=“110lll1”; WHEN“110”→>Y<=“101lll”; WHEN“111”=>Y<=“011ll1”; WHEN OTHERS→>Y<=“ XXXXXXXX”; END CASE END PROCESS: END behavior;
ARCHITECTURE behavior OF ymq83 IS SIGNAL INDATA:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN INDATA<=C&B&A; PROCESS(INDATA) BEGIN CASE INDATA IS WHEN “000” => Y<=“11111110”; WHEN “001” => Y<=“11111101”; WHEN “010” => Y<=“11111011”; WHEN “011” => Y<=“11110111”; WHEN “100” => Y<=“11101111”; WHEN “101” => Y<=“11011111”; WHEN “110” => Y<=“10111111”; WHEN “111” => Y<=“01111111”; WHEN OTHERS => Y<=“XXXXXXXX”; END CASE; END PROCESS; END behavior; 该描述 不具有 优先级 例1：设计3－8线译码器 译 码 器 设 计
四、运算器设计 例1:设计4位二进制加法器 LIBRARY IEEE: USE IEEESTD LOGIC 1164.ALLS USE IEEE STD LOGIC ARITHALL USE IEEE STD LOGIC UNSIGNEDALL: ENTITY ifq Is PORT a, b: IN STD LOGIC VECOR(3 DOWNTOO sum: OUTSTD LOGIC VECTOR(4 DOWNTOO) END jfq4: aRChITECTURE behavior oF ifg Is BEGIN 数据类 PROCESS(a, b) BEGIN 型必须 sum<=(0a)+(0&b); 致才 END PROCESS 能赋值 eNd behavior
四、运算器设计 例1：设计4位二进制加法器 数据类 型必须 一致才 能赋值 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY jfq4 IS PORT( a,b: IN STD_LOGIC_VECOR(3 DOWNTO 0); sum: OUT STD_LOGIC_VECTOR(4 DOWNTO 0)); END jfq4; ARCHITECTURE behavior OF jfq4 IS BEGIN PROCESS(a,b) BEGIN sum<=(‘0’&a)+(‘0’&b); END PROCESS; END behavior;