Outline 4.1 The y86 Instruction set Architecture 4.2 Logic Design and the hcl 4.3 Sequential y86 Implementations 4. 4 General Principles of pipelining 4.5 Pipelined y86 Implementations 4.6 Summary 2021/10/29 11
Outline • 4.1 The Y86 Instruction Set Architecture • 4.2 Logic Design and the HCL • 4.3 Sequential Y86 Implementations • 4.4 General Principles of Pipelining • 4.5 Pipelined Y86 Implementations • 4.6 Summary 2021/10/29 11
Problem 4.6(P273) Write an hcl expression for a signal xor, equal to the eXclusivE-or of nputs a and b. what is the relation between the signals xor and eg defined above bool eq =(la &&b)l(a&&!b) bool eq =(a &&b)l(a &&!b)) is it OK? The signals eq and xor will be complements of each other 2021/10/29
Problem 4.6 (P273) • Write an HCL expression for a signal xor, equal to the EXCLUSIVE-OR of inputs a and b. What is the relation between the signals xor and eq defined above ? 2021/10/29 12 bool eq = !((a && b) || (!a && !b)) is it OK? bool eq = (!a && b) || (a && !b) The signals eq and xor will be complements of each other
Problem 4.7(P263) Suppose you wal ba !eq31 Xor level equality cir b EXCLUSIVE-OR !e3 Problem 4.6 rat q equality circuits for a 32-bit wor level EXClUsiv b-1 additional logic( ao 2021/10/29
Problem 4.7 (P263) • Suppose you want to implement a wordlevel equality circuit using the EXCLUSIVE-OR circuits from Practice Problem 4.6 rather than from bit-level equality circuits. Design such a circuit for a 32-bit word consisting of 32 bitlevel EXCLUSIVE-OR circuits and two additional logic gates. 2021/10/29 13
Problem 4.8(P277) Write hcl code describing a circuit that for word inputs A, B, and C selects the median of the three values that is the output equals the word lying between the minimum and maximum of the three inputs int Med=[ A<=B&&b<=C: B: B<=A &&a<=C: A C 2021/10/29
Problem 4.8 (P277) • Write HCL code describing a circuit that for word inputs A, B, and C selects the median of the three values. That is, the output equals the word lying between the minimum and maximum of the three inputs. 2021/10/29 14 int Med3 = [ A <= B && B <= C : B; B <= A && A <= C : A; 1 : C: ];
Outline 4.1 The y86 Instruction set Architecture 4.2 Logic design and the HCL 4.3 Sequential y86 Implementations 4. 4 General Principles of pipelining 4.5 Pipelined y86 Implementations 4.6 Summary 2021/10/29
Outline • 4.1 The Y86 Instruction Set Architecture • 4.2 Logic Design and the HCL • 4.3 Sequential Y86 Implementations • 4.4 General Principles of Pipelining • 4.5 Pipelined Y86 Implementations • 4.6 Summary 2021/10/29 15