三种基本的数据相关 写后读相关( Read after write(RAW) I: add x1, x2 x3 由于实际的数据交换需求而引起的 了:subx4,x1,x3 读后写相关( Write After Read (WAr) 工:subx4,x1,x3 了:addx1,X2,x3 编译器编写者称之为“ anti-dependence”(反相关),是由于重复使用 寄存器名“x1”引起的 ·写后写相关( Write After write(WAW)) 工:subx1,x4,x3 j: add x1,x2, x3 编译器编写者称之为“ output dependence”,是由于重复使用寄存 器名“x1引起的 在后面的复杂的流水线中我们将会看到WAR和WAW相关 2/112021 chapter3. 17
三种基本的数据相关 • 写后读相关(Read After Write (RAW)) – 由于实际的数据交换需求而引起的 • 读后写相关（Write After Read (WAR) – 编译器编写者称之为“anti-dependence”（反相关），是由于重复使用 寄存器名“x1”引起的. • 写后写相关（Write After Write (WAW)） – 编译器编写者称之为“output dependence” ，也是由于重复使用寄存 器名 “x1”引起的. – 在后面的复杂的流水线中我们将会看到 WAR 和WAW 相关 2/11/2021 chapter3.17
消减数据相关的三种策略 连锁机制( Interlock) 在ise阶段保持当前相关指令,等待相关解除 设置旁路定向路径( Bypass or Forwarding) 只要结果可用,通过旁路尽快传递数据 投机( Speculate) 猜测一个值继续,如果猜测错了再更正
消减数据相关的三种策略 • 连锁机制（Interlock） – 在issue阶段保持当前相关指令，等待相关解除 • 设置旁路定向路径（Bypass or Forwarding) – 只要结果可用，通过旁路尽快传递数据 • 投机（Speculate） – 猜测一个值继续，如果猜测错了再更正 18
O Interlocking Versus Bypassing add x1, x3, 5 sub x2x1 x4 F‖D|X WIk add x1, x3, x5 FDXM bubble Instruction interlocked I D xMIw bubble in decode stage FDX M bubble F‖D1XM|W 1 x4 FD X add x1, x3, x5 Bypass around alu FDX w sub x2, xl, x4 with no bubbles 19
Interlocking Versus Bypassing 19 add x1, x3, x5 sub x2, x1, x4 F D add x1, x3, x5 F X D F sub x2, x1, x4 W M X bubble F D W X M W M W W M D X bubble M X bubble D F Instruction interlocked in decode stage F D X M W add x1, x3, x5 F D X M W sub x2, x1, x4 Bypass around ALU with no bubbles
Example Bypass Path Fe Decode EXecute Memory I Writeback Data Instruction bi Cache Cache
Fetch Decode EXecute Memory Example Bypass Path 20 Registers ALU B A Data Cache PC Instruction Cache Store Imm Inst. Register Writeback
Fully Bypassed Data Path Fetch Decode EXecute Memory Writeback Data 切 Instruction bi Cache Cache F||D×M|W L Assumes data written to registers FD XIIMIL W in a W cycle is readable in parallel D cycle( dotted line). Extra write F‖D data register and bypass paths F D MI W required if this is not possible
Fetch Decode EXecute Memory Fully Bypassed Data Path 21 Registers ALU B A Data Cache PC Instruction Cache Store Imm Inst. Register Writeback F D X M W F D X M W F D X M W F D X M W [ Assumes data written to registers in a W cycle is readable in parallel D cycle (dotted line). Extra write data register and bypass paths required if this is not possible. ]