End Ter 0603=0060"x0030 0805==0080×00501206=0.120"×0060 FIGURE 26.3 Example of passive component sizes(top view)( Productivity(NEPCON) Conferencel for information on industry uses of the latest SMT Pac overview of package styles is found in Appendix A of Hollomon [1995] and(for ICs only)in Signetics [1991b] which is being updated as of this writing Each IC manufacturer's data books will have packaging information for their products. The engineer should be familiar with the term"lead pitch", which means the center-to-center distance between IC leads Pitch may be in thousandths of an inch, also known as mils, or in millimeters. Common pitches are 0.050 in (50 mil pitch), 0.025 in. (25 mil pitch) frequently called"fine pitch, and 0.020 in. and smaller frequently called"ultra fine pitch". Metric equivalents are 1. 27 mm, 0.635 mm, and 0.508 mm and smaller. Conversions from metric to inches are easily approximated if one remembers that 1 mm approximately equals 40 mils For process control, design teams must consider the minimum and maximum package size variations allowed y their part suppliers, the moisture content of parts as-received, and the relative robustness of each lead type Incoming inspection should consist of both electrical and mechanical tests. Whether these are spot checks, lot checks, or no checks will depend on the relationship with the vendo 26.5 Substrate design guidelines As noted previously, substrate(typically PCB)design has an effect not only on board/component layout, but also on the actual manufacturing process. Incorrect land design or layout can negatively affect the placement process, the solder process, the test process or any combination of the three Substrate design must take into account the mix of SMDs that are available for use in manufacturing The considerations noted here as part of the design process are neither all-encompassing, nor in sufficient detail for a true SMT novice to adequately deal with all the issues involved in the process. They are intended to guide an engineer through the process, allowing him/her to access more detailed information as necessary. General references are noted at the end of this chapter, and specific references will be noted as applicable. In onferences such as the nepcon, and SMI are invaluable sources of information for both the and the experienced SMT engineer. Although these guidelines are noted as"steps", they are not necessarily in an absolute order, and may require several iterations back-and-forth among the steps to result in a final satisfactory process and product. After the circuit design(schematic capture)and analysis, Step l in the process is to determine whether all SMDs will be used in the final design making a Type I board, or whether a mix of SMDs and through-hole parts will be used, leading to a Type Il or Type III board. This decision will be governed by some or all of the Current parts stock Existence of current through-hole placement and/or wave solder equipment 2Surface Mount Technology Association, 5200 Wilson Rd, Suite 100, Minneapolis, MN 55424
© 2000 by CRC Press LLC Productivity (NEPCON) Conference1 for information on industry uses of the latest SMT packages. A good overview of package styles is found in Appendix A of Hollomon [1995] and (for ICs only) in Signetics [1991b] which is being updated as of this writing. Each IC manufacturer’s data books will have packaging information for their products. The engineer should be familiar with the term “lead pitch”, which means the center-to-center distance between IC leads. Pitch may be in thousandths of an inch, also known as mils, or in millimeters. Common pitches are 0.050 in. (50 mil pitch), 0.025 in. (25 mil pitch) frequently called “fine pitch”, and 0.020 in. and smaller frequently called “ultra- fine pitch”. Metric equivalents are 1.27 mm, 0.635 mm, and 0.508 mm and smaller. Conversions from metric to inches are easily approximated if one remembers that 1 mm approximately equals 40 mils. For process control, design teams must consider the minimum and maximum package size variations allowed by their part suppliers, the moisture content of parts as-received, and the relative robustness of each lead type. Incoming inspection should consist of both electrical and mechanical tests. Whether these are spot checks, lot checks, or no checks will depend on the relationship with the vendor. 26.5 Substrate Design Guidelines As noted previously, substrate (typically PCB) design has an effect not only on board/component layout, but also on the actual manufacturing process. Incorrect land design or layout can negatively affect the placement process, the solder process, the test process or any combination of the three. Substrate design must take into account the mix of SMDs that are available for use in manufacturing. The considerations noted here as part of the design process are neither all-encompassing, nor in sufficient detail for a true SMT novice to adequately deal with all the issues involved in the process. They are intended to guide an engineer through the process, allowing him/her to access more detailed information as necessary. General references are noted at the end of this chapter, and specific references will be noted as applicable. In addition, conferences such as the NEPCON, and SMI2 are invaluable sources of information for both the beginner and the experienced SMT engineer. Although these guidelines are noted as “steps”, they are not necessarily in an absolute order, and may require several iterations back-and-forth among the steps to result in a final satisfactory process and product. After the circuit design (schematic capture) and analysis, Step 1 in the process is to determine whether all SMDs will be used in the final design making a Type I board, or whether a mix of SMDs and through-hole parts will be used, leading to a Type II or Type III board. This decision will be governed by some or all of the following considerations: • Current parts stock • Existence of current through-hole placement and/or wave solder equipment 1 NEPCON, rep. by Reed Exhibition Co., Norwalk, CT. 2 Surface Mount Technology Association, 5200 Wilson Rd., Suite 100, Minneapolis, MN 55424. FIGURE 26.3 Example of passive component sizes (top view)(not to scale)
(Plastic Leaded Chip Camier) ual Row al outine Package) Quad Row hin Small ouing Packag时 <Qund Flatpack] FLATPACK FIGURE 26. 4 Examples of SMT plastic packages. Source: Intel Corporation, Packaging, Santa Clara Intel Corporation, 1994. with permissi
© 2000 by CRC Press LLC FIGURE 26.4 Examples of SMT plastic packages. (Source: Intel Corporation, Packaging, Santa Clara, Calif.: Intel Corporation, 1994. With permission.)
(a) FIGURE 26.5 (a)Footprint land and resist. Source: Phillips Semiconductors, Surface Mount Process and Application Notes, Sunnyvale, Calif. Phillips Semiconductors, 1991. With permission. )(b)QFP footprint. Source: Intel Corporation, Packaging, Santa Clara, Calif Intel Corporation, 1994. With permission Amortization of current through-hole placement and solder equipment Existence of reflow soldering equipment, or cost of new reflow soldering equipment Desired size of the final product Panellization of smaller Type I board Thermal issues related to high power circuit sections on the board It may be desirable to segment the board into areas based on function: RE, low power, high power, etc using all SMDs where appropriate, and mixed-technology components as needed. Power and connector portions of he circuit may point to the use of through-hole components, although as mentioned both these issues are ing addressed by circuit board material and connector manufacturers. Using one solder technique (reflow or wave) simplifies processing, and may outweigh other considerations. Step 2 in the SMT process is to define all the footprints of the SMDs under consideration for use in the design. The footprint is the copper pattern or land", on the circuit board upon which the SMd will be placed ootprint examples are shown in Figs. 26.5a and 26 5b, and footprint recommendations are available from IC manufacturers and in the appropriate data books. They are also available in various ECAd packages used for the design process, or in several references that include an overview of the SmT process[Electronic Packaging and Production, 1994. However, the reader is seriously cautioned about using the general references for anything other than the most common passive and active packages. Even the position of pin 1 may be different among IC manufacturers of the"same"chip. The footprint definition may also include the position of the solder resist pattern surrounding the copper pattern. Footprint definition sizing will vary depending on whether reflow or wave solder process is used. Wave solder footprints will require recognition of the direction of travel of the board through the wave, to minimize solder shadowing in the final fillet, as well as requirements for solder thieves. The copper footprint must allow for the formation of an appropriate, inspectable solder fillet. If done as part of the EDa process(electronic design automation, using appropriate electronic CAD software), the software will automatically assign copper directions to each component footprint, as well as appropriate coordinates and dimensions. These may need adjustment based on considerations related to wave soldering, test points, RF and/or power issues, and board production limitations. Allowing the software to select 5 mil traces when the board production facility to be used can only reliably do 10 mil traces would be inappropriat Likewise, the solder resist patterns must be governed by the production capabilities Final footprint and trace decisions will allow for optimal solder fillet formation ecessary trace and footprint area allow for adequate test points minimize board area, if appropriate set minimum inter-part clearances for placement and test equipment to safely access the board (Fig. 26.6) c 2000 by CRC Press LLC
© 2000 by CRC Press LLC • Amortization of current through-hole placement and solder equipment • Existence of reflow soldering equipment, or cost of new reflow soldering equipment • Desired size of the final product • Panellization of smaller Type I boards • Thermal issues related to high power circuit sections on the board It may be desirable to segment the board into areas based on function: RF, low power, high power, etc. using all SMDs where appropriate, and mixed-technology components as needed. Power and connector portions of the circuit may point to the use of through-hole components, although as mentioned both these issues are being addressed by circuit board material and connector manufacturers. Using one solder technique (reflow or wave) simplifies processing, and may outweigh other considerations. Step 2 in the SMT process is to define all the footprints of the SMDs under consideration for use in the design. The footprint is the copper pattern or “land”, on the circuit board upon which the SMD will be placed. Footprint examples are shown in Figs. 26.5a and 26.5b, and footprint recommendations are available from IC manufacturers and in the appropriate data books. They are also available in various ECAD packages used for the design process, or in several references that include an overview of the SMT process [Electronic Packaging and Production, 1994]. However, the reader is seriously cautioned about using the general references for anything other than the most common passive and active packages. Even the position of pin 1 may be different among IC manufacturers of the “same” chip. The footprint definition may also include the position of the solder resist pattern surrounding the copper pattern. Footprint definition sizing will vary depending on whether reflow or wave solder process is used. Wave solder footprints will require recognition of the direction of travel of the board through the wave, to minimize solder shadowing in the final fillet, as well as requirements for solder thieves. The copper footprint must allow for the formation of an appropriate, inspectable solder fillet. If done as part of the EDA process (electronic design automation, using appropriate electronic CAD software), the software will automatically assign copper directions to each component footprint, as well as appropriate coordinates and dimensions. These may need adjustment based on considerations related to wave soldering, test points, RF and/or power issues, and board production limitations. Allowing the software to select 5 mil traces when the board production facility to be used can only reliably do 10 mil traces would be inappropriate. Likewise, the solder resist patterns must be governed by the production capabilities. Final footprint and trace decisions will: • allow for optimal solder fillet formation • minimize necessary trace and footprint area • allow for adequate test points • minimize board area, if appropriate • set minimum inter-part clearances for placement and test equipment to safely access the board (Fig. 26.6) FIGURE 26.5 (a) Footprint land and resist. (Source: Phillips Semiconductors, Surface Mount Process and Application Notes, Sunnyvale, Calif.: Phillips Semiconductors, 1991.With permission.) (b) QFP footprint. (Source: Intel Corporation, Packaging, Santa Clara, Calif.: Intel Corporation, 1994. With permission.)