E Direct Memory Access (DMA) O tting Systems e CPU needs to address the device controllers to exchange data with them If request data one byte at a time, waste CPus time. G DMA controller has access to the system bus independent of the cpu. it contains several registers that can be written and read by the cpu 在低端(嵌入式)计算机中,通常不使用DMA,而让比DMA控制器快得多的 CPU直接做所有的工作。 Gao Haichang, Software School, Xidian University 13
Operating Systems Gao Haichang , Software School, Xidian University 13 Direct Memory Access (DMA) CPU needs to address the device controllers to exchange data with them. If request data one byte at a time, waste CPU’s time. DMA controller has access to the system bus independent of the CPU. It contains several registers that can be written and read by the CPU. 在低端（嵌入式）计算机中，通常不使用DMA，而让比DMA控制器快得多的 CPU直接做所有的工作
E Direct Memory Access (DMA) O tting Systems 日←D 1. CPU programs DMA Disk Main CPU the Dma controller controller memory controller Buffe Address Count Control4.Ack Interrupt when 2. DMA requests done transfer to memory 3. Data transferred ←Bus Operation of a DMa transfer Gao Haichang, Software School, Xidian University 14
Operating Systems Gao Haichang , Software School, Xidian University 14 Direct Memory Access (DMA) Operation of a DMA transfer
Operating Systems Interrupts Revisited Interrupt 1. Device is finished CPU 3. CPU acks controller interrupt Disk 表通 Keyboard Clock 2. Controller Printer Issues Interrupt Bus How interrupts happens The connections between the devices and the interrupt controller actually use interrupt lines on the bus rather than dedicated wires. Gao Haichang, Software School, Xidian University 15
Operating Systems Gao Haichang , Software School, Xidian University 15 Interrupts Revisited How interrupts happens. The connections between the devices and the interrupt controller actually use interrupt lines on the bus rather than dedicated wires. Bus
Operating Systems CA Interrupts Revisited g When an lo device has finished the work given to it, it causes an interrupt. The signal is detected by the interrupt controller chip on the parentboard. If no other interrupts are pending, the interrupt controller processes the interrupt immediately. g To handle the interrupt, the controller puts a number on the address lines specifying which device wants attention and asserts a signal that interrupts the cpu The interrupt signal causes the cpu to stop what it is doing and start doing sth else. Gao Haichang, Software School, Xidian University 16
Operating Systems Gao Haichang , Software School, Xidian University 16 Interrupts Revisited When an I/O device has finished the work given to it, it causes an interrupt. The signal is detected by the interrupt controller chip on the parentboard. If no other interrupts are pending, the interrupt controller processes the interrupt immediately. To handle the interrupt, the controller puts a number on the address lines specifying which device wants attention and asserts a signal that interrupts the CPU. The interrupt signal causes the CPU to stop what it is doing and start doing sth else
Operating Systems Chapter 5: Input/Output 51 Principles of l/o hardwareⅣO硬件原理 5,2 Principles of lo softwareⅣO软件原理 4 5.3 10 software layers IO软件层次 H 5.4 Disks 盘 H 5.5 Clocks 时钟 56 Character- oriented terminals面向字符的终端 57 Graphical user interfaces图形用户界面 a 5.8 Network terminals 网络终端 耳59 Power management 电源管理 Gao Haichang, Software School, Xidian University 17
Operating Systems Gao Haichang , Software School, Xidian University 17 Chapter 5: Input/Output 5.1 Principles of I/O hardware I/O硬件原理 5.2 Principles of I/O software I/O软件原理 5.3 I/O software layers I/O软件层次 5.4 Disks 盘 5.5 Clocks 时钟 5.6 Character-oriented terminals 面向字符的终端 5.7 Graphical user interfaces 图形用户界面 5.8 Network terminals 网络终端 5.9 Power management 电源管理