tO Example on MSI Cache Coherence Request Processor P1 Processor p2 BU Memory State Addr value State Addr Value Proc Addr Action Addr value P1: Write 10 to A1 P1 A1 Wr Miss A1 15 MA110 P1: Read A1(Hit) M A1 10 P2: Read A1 P2 A1 Rd miss SA110 P1 A1 Wr Back A1 10 s A1 10 P2 A1 Transfer P2: Write 20 to a1 P2 A1 Invalidate A110 MA120 A110 P2: Write 40 to A2 MA240 A225 Assume that a1 and a2 map to same cache block Initial cache state is invalid 2021/2/1 计算机体系结构
Example on MSI Cache Coherence 2021/2/1 计算机体系结构 7 • Assume that A1 and A2 map to same cache block • Initial cache state is invalid
Write-back Cache Cachet块状态 PrRd/- Invalid, Valid(clean), Modified(dirty PwR/ Processor/ Cache操作 PrRd, PrWr, block Replace M 总线事务 Bus read(BusRd), Write-Back BusWB) PrWr/- 仅传送 cache-b|ock Replace/BusWB PwR/BusRd 针对 Cache-致性的块状态调整 Replace/ Treat valid as shared PrRd/- Treat modified as Exclusive PrRd/BusRd ·引入新的总线事务 Bus Read-eXclusive(BusRdX) 其基本动作是:读进并修改 2021/2/1 计算机体系结构
Write-back Cache • Cache块状态 – Invalid, Valid (clean), Modified (dirty) • Processor / Cache 操作 – PrRd, PrWr, block Replace • 总线事务 – Bus Read (BusRd), Write-Back (BusWB) – 仅传送cache-block • 针对Cache一致性的块状态调整 – Treat Valid as Shared – Treat Modified as Exclusive • 引入新的总线事务 – Bus Read-eXclusive (BusRdX) – 其基本动作是：读进并修改 2021/2/1 计算机体系结构 8 PrRd/— PrWr/— V M I Replace/BusWB PrWr/— PrRd/BusRd Replace/— PrWr/BusRd PrRd/—
MSI Write-Back Invalidate Protocol 3 states. Modified:仅该 cache拥有修改过的、有效的该 Prrd/- 块 copy PwR Shared:该块是干净块,其他 cache中也可能含 有该块,存储器中的内容是最新的 M valid:该块是无效块( invalid) ·4 bus transactions: Bus read:读失效时产生 BUsRd总线事务 PrWr/Bus Rdx Bus Rd/Flush Bus read exclusive(总线排他读): BusRdX Pwr/BusRo Bus RdXFlush ·得到独占的( exclusive) cache b|ock s Replace /Bus We 其基本动作为读进并修改 Bus write-Back: BUsWB用于 cache块的替换 PrRd/Bus rd Bus RdX/- PrRd/ Replace- Flush on busrd or busrdX BusRd/- · Cache将数据块放到总线上(而不是从存储器取数 据)完成 Cache-to-cache的传送,并更新存储器 2021/2/1 计算机体系结构
MSI Write-Back Invalidate Protocol • 3 states: – Modified: 仅该cache拥有修改过的、有效的该 块copy – Shared: 该块是干净块，其他cache中也可能含 有该块，存储器中的内容是最新的 – Invalid: 该块是无效块（invalid） • 4 bus transactions: – Bus Read: 读失效时产生BusRd总线事务 – Bus Read Exclusive（总线排他读）: BusRdX • 得到独占的（exclusive）cache block • 其基本动作为读进并修改 – Bus Write-Back: BusWB用于cache 块的替换 – Flush on BusRd or BusRdX • Cache将数据块放到总线上（而不是从存储器取数 据）完成 Cache-to-cache的传送，并更新存储器 2021/2/1 计算机体系结构 9 M I S PrRd/— PrWr/— PrRd/BusRd PrWr/BusRdX PrWr/BusRdX PrRd/— BusRd/— BusRd/Flush BusRdX/Flush Replace/BusWB BusRdX/— Replace/—
State Transitions in the msI Protocol Processor read Cache miss→产生 BusRd事务 PrRd/- Cache hit(sorM)→无总线动作 Processor Write 当在非 Modified0态时,产生总线 BusRdX事务, BusRdX导致其他 Cache中 的对应块作废( invalidate 当在 Modified状态时,无总线动作 PrWr/Bus rdX Bus Rd/ flush observing a Bus read PrWr/Bus Rd BUs RdX/Flush Replace/BusWB 如果该块是 Modified,产生Fush总线事务 更新存储器和有需求的 Cache PrRd/Bus rd BusRdX/- ·引起总线事务的 Cache块状态→> Shared PrRdl Replace/- observing a bus read exclusive BusRd/- 作废相关b|ock 如果该块是 modified,产生 Flush总线事务 2021/2/1 计算机体系结构
State Transitions in the MSI Protocol • Processor Read – Cache miss 产生BusRd事务 – Cache hit (S or M) 无总线动作 • Processor Write – 当在非Modified状态时，产生总线 BusRdX事务，BusRdX导致其他Cache中 的对应块作废（invalidate） – 当在Modified状态时，无总线动作 • Observing a Bus Read – 如果该块是 Modified, 产生Flush总线事务 • 更新存储器和有需求的Cache • 引起总线事务的Cache块状态 Shared • Observing a Bus Read Exclusive – 作废相关block – 如果该块是modified, 产生Flush总线事务 2021/2/1 计算机体系结构 10 M I S PrRd/— PrWr/— PrRd/BusRd PrWr/BusRdX PrWr/BusRdX PrRd/— BusRd/— BusRd/Flush BusRdX/Flush Replace/BusWB BusRdX/— Replace/—
◎ Example on Msi Write-Back Protocol PrRd/- PrWr/ P us 7 PrWr/Bus rdx bus rd/flush、 PrWr/BusRdX Bus RdX/Flush Replace/ BusWE Memory PrRd/BusRd PrRd/-Replacel- BusRdX— yO devices 7 Processor Action State P1 State p2 State P3 Bus Action Data from 1. 1 reads u Busrd Memory 2 P3 reads u BusRd Memory 3. P3 writes u BusRdX Memory 4. P1 reads u BusRd. flush P3 cache 5. P2 reads u s BusRd Memory 2021/2/1 计算机体系结构
Example on MSI Write-Back Protocol 2021/2/1 计算机体系结构 11 Memory I/O devices u: P1 P2 P3 u S 75 u S 7 u MS 57 1. P1 reads u S BusRd Memory 2. P3 reads u S S BusRd Memory 3. P3 writes u I M BusRdX Memory 4. P1 reads u S S BusRd, Flush P3 cache 5. P2 reads u S S S BusRd Memory Processor Action State P1 State P2 State P3 Bus Action Data from 5 7 IS S M I S PrRd/— PrWr/— PrRd/BusRd PrWr/BusRdX PrWr/BusRdX PrRd/— BusRd/— BusRd/Flush BusRdX/Flush Replace/BusWB BusRdX/— Replace/—