Different Masks Sets ew masks made to order for one design all masks made to order for one design most masks shaed with oner designs unprocessed preprocessed waler waler a b) Full-custom Semi-custom 2021/1/13 ASIC Design,by Yan Bo 17
ASIC Design, by Yan Bo 17 Different Masks Sets Full-custom Semi-custom 2021/1/13
The compositions of electronic system separate component:resistor,capacitor,inductor,diode,transistor,etc Standard IC Generic Standard SSI,MSI,LSI,VLSI (Generic Integrated Circuit)Application Specific Standard Parts Full custom Semicustom gate array Specific IC standard cell (Application Specific IC) Programmable Logic Array Simple PLD Programmable Array Logic Generic Array Logic Programmable Logic Device Complex PLD Field Programmable Gate Array Printed-Circuit Board Field Programmable System on Chip 2021/1/13 ASIC Design,by Yan Bo 18
ASIC Design, by Yan Bo The compositions of electronic system Standard IC (Generic Integrated Circuit) separate component: resistor, capacitor, inductor, diode, transistor, etc Specific IC (Application Specific IC) Generic Standard SSI, MSI, LSI, VLSI Full custom Semi custom Programmable Logic Device gate array standard cell Simple PLD Field Programmable Gate Array Field Programmable System on Chip Complex PLD Programmable Logic Array Programmable Array Logic Generic Array Logic Printed-Circuit Board Application Specific Standard Parts 2021/1/13 18
Programmability of PLDs Product terms Programmable Block AND Plane OR Plane Inputs AND Plane OR Plane Outputs ROM NA P PLA P P PAL P NP NA not applicable,P programmable, NP not programmable. 与平面 输入 (n×p) VDD mn-1 n乘积项 或平面 (D×m) 上拉电阻 PAL-like PAL-like 上拉电阻 O/T block block Interconnection wires 品体管连接 PAL-like PAL-like block nbar block 下拉品体管字线 xpoiq O/I ourm-11 输出（位线） 2021/1/13 ASIC Design,by Yan Bo 19
ASIC Design, by Yan Bo Programmability of PLDs 2021/1/13 19
ROM 2 Minterms (Word lines) formed from inputs 输出级冲器 数 addr[] 地址译码器 addr[1] Address decoder OR memory 存储矩阵 〉 : array (2”×m) 出 addr[n-1] (Nonprogrammable) A n inputs D[m-1] D[o] m outputs(Bit lines) 三态控制 与平面 输入 (n×p) 乘积项 或平面 (p x m) 输入码字 输出码字 上拉电 上拉电阻 -Data_Out (n-1] 000 10000000 001 01000000 Data In 010 00100000 011 00010000 2 100 00001000 译码器 101 00000100 Data_Ou 品体管连接 110 00000010 111 00000001 En_bar 下拉品休管学线 -1 our[o 输出（位线） 2021/1/13 ASIC Design,by Yan Bo 20
ASIC Design, by Yan Bo ROM 2021/1/13 20
Programmable Logic Array Example A B C D Programmable Block AND Plane OR Plane AB ROM NA P PLA P A'B' PAL P NP NA not applicable,P programmable, NP not programmable. CD' C'D Notation for Implementing FO=AB AB' F1=CD'C'D FO F1 2021/1/13 ASIC Design,by Yan Bo 21
ASIC Design, by Yan Bo Notation for Implementing F0 = A B + A' B' F1 = C D' + C' D F0 F1 AB A'B' CD' C'D A B C D Programmable Logic Array Example 2021/1/13 21