CS314ComputerOrganizationFall2017Chapter5A:ExploitingtheMemoryHierarchy,Part1Haojin ZhuProfessor[AdaptedfromComputerOrganizationandDesign,4thEdition,CS314Chapter5A.1HaojinZhu, SJTU, 2017
CS314 Chapter 5A.1 Haojin Zhu, SJTU, 2017 CS 314 Computer Organization Fall 2017 Chapter 5A: Exploiting the Memory Hierarchy, Part 1 Haojin Zhu Professor [Adapted from Computer Organization and Design, 4th Edition
Review:Major Components of a ComputerProcessorDevicesControlInputMemoryDatapathOutputMainMemoryCacheSecondaryMemory(Disk)CS314Chapter5A.2HaojinZhu, SJTU,2017
CS314 Chapter 5A.2 Haojin Zhu, SJTU, 2017 Review: Major Components of a Computer Processor Control Datapath Memory Devices Input Output Cache Memory Main Secondary Memory (Disk)
The“MemoryWall” Processor vs DRAM speed disparity continues to grow1000Ss10010Core-Memory0.10.012010+VAX/1980PPro/1996 Good memory hierarchy (cache) design is increasinglyimportant to overall performanceCS314Chapter5A.4Haojin Zhu, SJTU,2017
CS314 Chapter 5A.4 Haojin Zhu, SJTU, 2017 The “Memory Wall” ❑ Processor vs DRAM speed disparity continues to grow 0.01 0.1 1 10 100 1000 VAX/1980 PPro/1996 2010+ Core Memory Clocks per instruction Clocks per DRAM access ❑ Good memory hierarchy (cache) design is increasingly important to overall performance
The Memory Hierarchy Goal Fact: Large memories are slow and fast memories aresmall How do we create a memory that gives the illusion ofbeing large, cheap and fast (most of the time)?WithhierarchyWithparallelismCS314Chapter5A.5HaojinZhu,SJTU,2017
CS314 Chapter 5A.5 Haojin Zhu, SJTU, 2017 The Memory Hierarchy Goal ❑ Fact: Large memories are slow and fast memories are small ❑ How do we create a memory that gives the illusion of being large, cheap and fast (most of the time)? With hierarchy With parallelism
ATvpicalMemoryHierarchy Take advantage of the principle of locality to present theuser with as much memory as is available in thecheapest technology at the speed offered by the fastesttechnologyOn-ChipComponentsControlSecondarySecondMainMemoryLevelMemory(Disk)DatapathRegFiCache(DRAM)(SRAM)B元1's10's100's10,000'sSpeed(%cycles):V's100'sM'sG'sT's10K'sSize (bytes):Cost:lowesthighestCS314Chapter5A.6HaojinZhu, SJTU, 2017
CS314 Chapter 5A.6 Haojin Zhu, SJTU, 2017 Second Level Cache (SRAM) A Typical Memory Hierarchy Control Datapath Secondary Memory (Disk) On-Chip Components RegFile Main Memory (DRAM) Data Cache Instr Cache ITLB DTLB Speed (%cycles): ½’s 1’s 10’s 100’s 10,000’s Size (bytes): 100’s 10K’s M’s G’s T’s Cost: highest lowest ❑ Take advantage of the principle of locality to present the user with as much memory as is available in the cheapest technology at the speed offered by the fastest technology