GOALS OF THIS LECTURE-We will implement a subset of Mips instructions using single clockcycle.-Simple subset,shows most aspects-Memoryreference:lw,sw-Arithmetic/logical: add, sub,and,or, s1t-Control transfer:beq,j
▪We will implement a subset of MIPS instructions using single clock cycle. ▪Simple subset, shows most aspects ▪ Memory reference: lw, sw ▪ Arithmetic/logical: add, sub, and, or, slt ▪ Control transfer: beq, j
INSTRUCTION PROCESSINGFetch instruction from memoryDecodeinstructionEvaluateaddressFetchoperandsfrommemoryExecuteoperationStoreresult
Decode instruction Evaluate address Fetch operands from memory Execute operation Store result Fetch instruction from memory
INSTRUCTION EXECUTION-The first two steps are the same for all instructions:-PC→instructionmemory,fetchinstruction-PC←PC+4-Decode the instruction: The operation and operands (register numbersimmediate,targetaddress)-DependingontheinstructionclassUseALUtocalculate-Arithmetic-logicalresult-Memoryaddress forload/storeBranchtarget address-Accessdatamemoryforload/store-PC←target address
▪The first two steps are the same for all instructions: ▪ PC → instruction memory, fetch instruction ▪ PC PC + 4 ▪ Decode the instruction: The operation and operands (register numbers, immediate, target address) ▪Depending on the instruction class ▪ Use ALU to calculate ▪ Arithmetic-logical result ▪ Memory address for load/store ▪ Branch target address ▪ Access data memory for load/store ▪ PC target address
CPU OVERVIEWAddAddDataRegister#ALUHAddressPCAddressRegistersInstructionRegister#DataInstructionmemorymemoryRegister#Data
MUTIPLEXERSCan't just joinwires togetherUse multiplexersAddDataRegister#AddressALUPCAddressRegistersInstructionRegister#DataInstructionmemoryRegister#memoryData
◼ Can’t just join wires together ◼ Use multiplexers