Turn on some Max+Plus l option There are some built-in Option to assist the engineer during the Vhdl design stage Syntax Color Option from the option menu o MAX+plus ll- d: \max2work \a MAX+plus ll Eile Edit Iemplates Assign Utilities Optionswindow Help 口回国画回图fes Tab SI E test. vhd-Text Editor Auto-Indent entity test主s Turn on User Libraries this option out std logic) architecutre a of test is Color Palette begin Authorization Code b<= not Preferences. nd a Copyright 1997 Altera Corporation Reserve word in Blue 2/22/2021P11 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.11 Turn on some Max+Plus II Option ◼ There are some built-in Option to assist the engineer during the VHDL design stage – Syntax Color Option from the Option menu Turn on this option Reserve word in Blue
User can modify the Color Option use the color palette under Option menu to customize the color of comments, Illegal characters, megafunctions macrofuncitons MAX+plus ll Eile Edit Templates Assign Utilities Options window Help 口圖倒圖画圖回國Eont AA 國 test.vhd-T entity test ScreenElements Colors set with Control panel Select port(a- pplication workspace window Background b -1 Select Color Element chitecutr 「 Application worksp rawing sheet bordet b < not a MAX+PLUS II Colors Copyright 1997 Altera Corporation Cancel 2/22/2021P12 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.12 User can modify the Color Option ◼ use the Color Palette under Option Menu to customize the color of – comments, illegal characters, megafunctions, macrofuncitons…. Select Element Select Color
Error Location during Compilation Easy to locate the error Error location 國 test.whd- TextEditor 口区 Compiler Database entity test is Netlist Builder port (a in bit; Assembler Extractor b out bit) end test architecture a test b < not a nd a 4I Messages-Compiler Line 8: File d: \max2worktest e, but found Click Info: Information on Architecture TES I-A was not storea th e erro Message卜1of2 Locate in Floorplan Editor Help on Message message Locate 0 of 1 L ocate All Locate the error Copyright 1997 Altera Corporation 2/22/2021P13 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.13 Error Location during Compilation ◼ Easy to locate the error Click on the error message Locate the error Error location
VHDL Template If-then-else id MAX+plus ll -d: \max 2work \test MAX+plus l Eile.VHDL Template forgot case-end case loop-end loop Overall Structure Full Design: Counter Full desinn flin E test. vhd-Text Editor IF expression THEN statement ELS expression THEN statement SE statement ement; END Modify the code as user want Copyright 1997 Altera Corporation 2/22/2021P14 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.14 VHDL Template I forgot ……. If-then-else case-end case loop-end loop ??…??? Modify the code as user want
General vhdl Format 1O port define ENTITY test Is Key word section PORT Input_pin_name: IN bit output pin name: OUT bit) VHDL Format ZEND test IRCHITECTURE test body OF test IS Must be the same - Logic BEGIN as the save TEST VHD output pin name <=input_pin_ name file ENd test body This two must be the same Logic behaviour define section Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.15 General VHDL Format ENTITY test IS PORT ( input_pin_name : IN bit; output_pin_name : OUT bit); END test; ARCHITECTURE test_body OF test IS BEGIN output_pin_name <= input_pin_name; END test_body; Key Word VHDL Format Logic This two must be the same I/O port define section Logic Behaviour define section Must be the same as the save TEST.VHD file