■ create your VHDL file Fe Untitled2- Text Editor entity test is port ( a: in std logic; b:out std logic); architecutre a of test is begin b < not a. end a? Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.6 ◼ create your VHDL file
u save your Vhdl file as name. VHD Qo MAX+plus -d: \ max2work \a MAN+plus Eile Edit Iemplates Assign Utilities The name must be the same entity test port (a: in std logic; b: out std logic) architecutre a of test is begin b<= not a: Save As Directory is: d: \ max2work segment. tdf or advan. tdf ax2work decoder tdf flip flop tdf Drives. Ipm mult1. tdf Automatic Extension tdf Copyright 1997 Altera Corporation OK 2/22/2021P7 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.7 ◼ save your VHDL file as name.VHD The name must be the same
Select the Standard Version of VHDL coding 1987or1993 o MAX+plus II-c: \max2work \vhdL \ adder HDL Netlist Reader Settings AX+plus ll File Processing Interfaces Assign Options Window ! VHDL Version 囗圖圖国国 EDIF Netlist Reader Settings C VHDL 1987 C VHDL 1993 EDIF Netlist writer EDIF Netlist Writer Settings Project Libraries Verilog Netlist Writer Compiler Verilog Netlist Writer Settings Directory Name Compiler VHD) Netist Reader Seting. i: mam2work Directorie Netlist /HDL Netlist writer Select which Extractor VHDL Netlist writer Settings version you XNF Netlist Reader Settings want Existing Synopsys Compiler Syrippsys Compiler Settings Start Cancel Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.8 ◼ Select the Standard Version of VHDL coding – 1987 or 1993 Select which version you want
■ Compile your VHDL file MA+plus ll File Processing Interfaces Assign Options window Help 回圖 囚國國鬯國圖啁闔圖 Partitioner start 女Me Warning: Timing characteristics of device EPF MAX+plus ll -Compiler Project compilation was successful 4 Message o of 1 K Help on Message k Locate>0 of 0 i ocate Ail Copyright 1997 Altera Corporation DONE 2/22/2021P
Copyright © 1997 Altera Corporation 2/22/2021 P.9 ◼ Compile your VHDL file DONE !
Bonus Topic may help for VHDL Design within Max+PIus‖ Copyright 1997 Altera Corporation 2/22/2021P10 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.10 Bonus Topic may help for VHDL Design within Max+Plus II