Getting Started:Creating Applications with uVision 21 C166,XE166,XC2000 Development Tool Support The Keil C166 Compiler supports all C166,XE166,XC2000 specific features and provides additional extensions such as: Memory type support and flexible digital pattern processing for extremely fast variable access Function inlining eliminating call/return overhead Inline assembly for accessing all microcontroller and MAC instructions ARM7 and ARM9 based Microcontrollers The ARM7 and ARM9 based microcontrollers run on a load-store RISC architecture with 32-bit registers and fixed op-code length.The architecture provides a linear 4GB memory address space.In contrast to the previously mentioned 8/16-bit devices,no specific memory types are provided,since memory addressing is performed via 32-bit pointers in microcontroller registers. Peripheral registers are mapped directly into the linear address space.The Thumb instruction set improves code density by providing a compressed 16-bit instruction subset. The ARM7 and ARM9 cores are easy to use,cost-effective,and support modern object-oriented programming techniques.They include a 2-level interrupt system with a normal interrupt(IRQ)and a fast interrupt(FIQ)vector.To minimize interrupt overhead,typical ARM7/ARM9 microcontrollers provide a vectored interrupt controller.The microcontroller operating modes,separate stack spaces, and Software Interrupt(SVC)features produce efficient use of Real-Time Operating Systems. The ARM7 and ARM9 core provides thirteen general-purpose registers(RO- R12),the stack pointer(SP)R13,the link register(LR)R14,which holds return addresses on function calls,the program counter(PC)R15,and a program status register(PSR).Shadow registers,available in various operating modes,are similar to register banks and reduce interrupt latency
Getting Started: Creating Applications with µVision 21 C166, XE166, XC2000 Development Tool Support The Keil C166 Compiler supports all C166, XE166, XC2000 specific features and provides additional extensions such as: Memory type support and flexible digital pattern processing for extremely fast variable access Function inlining eliminating call/return overhead Inline assembly for accessing all microcontroller and MAC instructions ARM7 and ARM9 based Microcontrollers The ARM7 and ARM9 based microcontrollers run on a load-store RISC architecture with 32-bit registers and fixed op-code length. The architecture provides a linear 4GB memory address space. In contrast to the previously mentioned 8/16-bit devices, no specific memory types are provided, since memory addressing is performed via 32-bit pointers in microcontroller registers. Peripheral registers are mapped directly into the linear address space. The Thumb instruction set improves code density by providing a compressed 16-bit instruction subset. The ARM7 and ARM9 cores are easy to use, cost-effective, and support modern object-oriented programming techniques. They include a 2-level interrupt system with a normal interrupt (IRQ) and a fast interrupt (FIQ) vector. To minimize interrupt overhead, typical ARM7/ARM9 microcontrollers provide a vectored interrupt controller. The microcontroller operating modes, separate stack spaces, and Software Interrupt (SVC) features produce efficient use of Real-Time Operating Systems. The ARM7 and ARM9 core provides thirteen general-purpose registers (R0– R12), the stack pointer (SP) R13, the link register (LR) R14, which holds return addresses on function calls, the program counter (PC) R15, and a program status register (PSR). Shadow registers, available in various operating modes, are similar to register banks and reduce interrupt latency
22 Chapter 2.Microcontroller Architectures R1 ARM7 and ARM9 Operation Modes R2 R3 User Normal execution state FIQ Fast Interrupt mode R4 IRQ Interrupt mode R5 SVC Supervisor mode(software interrupt) R6 UND Undefined instruction execution ABT Memory access failure ⑧ R8 R8 R9 R9 R10 R10 R11 R11 R12 R12 R13=SP R13=SP R13=SP R13=SP R13=SP R13=SP R14=LR R14=LR R14=LR R14=LR R14=LR R14=LR R15=PC CPSR SPSR SPSR SPSR SPSR SPSR User FIQ IRQ SVC ABT UND ARM7 and ARM9 Highlights Linear 4 GB memory space that includes peripherals and eliminates the need for specific memory types Load-store architecture with efficient pointer addressing.Fast task context switch times are achieved with multiple register load/store Standard(IRQ)and Fast(FIQ)interrupt.Banked microcontroller registers on FIQ reduce register save/restore overhead Vectored Interrupt Controller(available in most microcontrollers) optimizes multiple interrupt handling Processor modes with separate interrupt stacks for predictable stack requirements Compact 16-bit Instruction Set (Thumb).Compared to ARM mode, Thumb mode code is about 65%of the code size and 160%faster when executing from a 16-bit memory system
22 Chapter 2. Microcontroller Architectures R1 R15 = PC R14 = LR R13 = SP R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 CPSR User R14 = LR R13 = SP R12 R11 R10 R9 R8 SPSR FIQ R14 = LR R13 = SP SPSR IRQ R14 = LR R13 = SP SPSR SVC R14 = LR R13 = SP SPSR ABT R14 = LR R13 = SP SPSR UND ARM7 and ARM9 Operation Modes User Normal execution state FIQ Fast Interrupt mode IRQ Interrupt mode SVC Supervisor mode (software interrupt) ABT Memory access failure UND Undefined instruction execution ARM7 and ARM9 Highlights Linear 4 GB memory space that includes peripherals and eliminates the need for specific memory types Load-store architecture with efficient pointer addressing. Fast task context switch times are achieved with multiple register load/store. Standard (IRQ) and Fast (FIQ) interrupt. Banked microcontroller registers on FIQ reduce register save/restore overhead. Vectored Interrupt Controller (available in most microcontrollers) optimizes multiple interrupt handling Processor modes with separate interrupt stacks for predictable stack requirements Compact 16-bit Instruction Set (Thumb). Compared to ARM mode, Thumb mode code is about 65% of the code size and 160% faster when executing from a 16-bit memory system
Getting Started:Creating Applications with uVision 23 ARM7 and ARM9 Development Tool Support The ARM compilation tools support all ARM-specific features and provide Function Inlining eliminates call/return overhead and optimizes parameter passing Inline assembly supports special ARM/Thumb instructions in C/C++ programs RAM functions enable high-speed interrupt code and In-System Flash programming ARM/Thumb interworking provides outstanding code density and microcontroller performance Task function and RTOS support are built into the C/C++compiler Cortex-Mx based Microcontrollers Designed for the 32-bit microcontroller market,the Cortex-Mx microcontrollers combine excellent performance at low gate count with features only previously found in high-end processors. With 4GB of linear,unified memory space,the Cortex-Mx processors provide bit-banding features and supports big and little endian configuration.Predefined memory types are available,while some memory regions have additional attributes.Code can be located in the SRAM,external RAM,but preferably in the Code region.Peripheral registers are mapped into the memory space.Code density is improved by the Thumb or Thumb2 instruction set,depending on the processor version. General-purpose registers rank from RO to R12.R13(SP)is banked,with only one copy of the R13(MSP,PSP)being visible at a time.Special registers are available,but are not used for normal data processing.Some of the 16-bit Thumb instructions can access RO-R7(low)registers only.There is no FIQ; however,nested interrupts and interrupt priority handling is implemented via the Nested Vector Interrupt Controller(NVIC),greatly reducing interrupt latency
Getting Started: Creating Applications with µVision 23 ARM7 and ARM9 Development Tool Support The ARM compilation tools support all ARM-specific features and provide: Function Inlining eliminates call/return overhead and optimizes parameter passing Inline assembly supports special ARM/Thumb instructions in C/C++ programs RAM functions enable high-speed interrupt code and In-System Flash programming ARM/Thumb interworking provides outstanding code density and microcontroller performance Task function and RTOS support are built into the C/C++ compiler Cortex-Mx based Microcontrollers Designed for the 32-bit microcontroller market, the Cortex-Mx microcontrollers combine excellent performance at low gate count with features only previously found in high-end processors. With 4GB of linear, unified memory space, the Cortex-Mx processors provide bit-banding features and supports big and little endian configuration. Predefined memory types are available, while some memory regions have additional attributes. Code can be located in the SRAM, external RAM, but preferably in the Code region. Peripheral registers are mapped into the memory space. Code density is improved by the Thumb or Thumb2 instruction set, depending on the processor version. General-purpose registers rank from R0 to R12. R13 (SP) is banked, with only one copy of the R13 (MSP, PSP) being visible at a time. Special registers are available, but are not used for normal data processing. Some of the 16-bit Thumb instructions can access R0-R7 (low) registers only. There is no FIQ; however, nested interrupts and interrupt priority handling is implemented via the Nested Vector Interrupt Controller (NVIC), greatly reducing interrupt latency
24 Chapter 2.Microcontroller Architectures Cortex Core Register Set RO R1 R2 R3 Low Registers R4 R5 R6 General-Purpose Registers R7 R8 R9 R10 High Registers R11 R12 R13=PSP R13=MSP Process Stack Pointer (PSP),Main Stack Pointer(MSP):(banked) R14=LR Link Register R15=PC Program Counter xPSR Program Status Register PRIMASK FAULTMASK Exoeption Mask Registers Special Registers BASEPRI CONTROL Control Registers Cortex-Mx Highlights Nested Vectored Interrupt Controller optimizes multiple external interrupts(up to 240+1 NMI,with at least eight priority levels) a RO-R3,R12,LR,PSR,and PC are pushed automatically to the stack at interrupt entry and popped back at interrupt exit points Only one instruction set(Thumb2),assuring software upward compatibility with the entire ARM roadmap Several Extreme Low-Power Modes with an attached Wake-Up Interrupt Controller (WIC)
24 Chapter 2. Microcontroller Architectures R15 = PC R14 = LR R13 = MSP R12 R11 R10 R9 R8 CONTROL BASEPRI FAULTMASK PRIMASK R13 = PSP Control Registers Process Stack Pointer (PSP), Main Stack Pointer (MSP): (banked) Cortex Core Register Set R1 R7 R6 R5 R4 R3 R2 R0 General-Purpose Registers Low Registers High Registers Link Register Program Counter Exception Mask Registers Special Registers xPSR Program Status Register Cortex-Mx Highlights Nested Vectored Interrupt Controller optimizes multiple external interrupts (up to 240 + 1 NMI, with at least eight priority levels) R0-R3, R12, LR, PSR, and PC are pushed automatically to the stack at interrupt entry and popped back at interrupt exit points Only one instruction set (Thumb2), assuring software upward compatibility with the entire ARM roadmap Several Extreme Low-Power Modes with an attached Wake-Up Interrupt Controller (WIC)
Getting Started:Creating Applications with uVision 25 Cortex-Mx Development Tool Support In addition to the ARM specific characteristics,the Keil MDK-ARM supports the Cortex-Mx Microcontroller Software Interface Standard(CMSIS)and provides the following features: Core registers and core peripherals are accessible through C/C++ functions Device independent debug channel for RTOS kernels Supports object oriented programming,reuse of code,and implements an easy way of porting code to different devices Extensive debug capabilities allowing direct access to memory without stopping the processor CMSIS is supported,making the software compatible across the Cortex-Mx architectures Architecture Comparison Conclusions The various architectures have pros and cons and the optimal choice depends highly on the application requirements.The following code comparison section provides additional architectural information that can help you in selecting the optimal microcontroller for your target embedded system
Getting Started: Creating Applications with µVision 25 Cortex-Mx Development Tool Support In addition to the ARM specific characteristics, the Keil MDK-ARM supports the Cortex-Mx Microcontroller Software Interface Standard (CMSIS) and provides the following features: Core registers and core peripherals are accessible through C/C++ functions Device independent debug channel for RTOS kernels Supports object oriented programming, reuse of code, and implements an easy way of porting code to different devices Extensive debug capabilities allowing direct access to memory without stopping the processor CMSIS is supported, making the software compatible across the Cortex-Mx architectures Architecture Comparison Conclusions The various architectures have pros and cons and the optimal choice depends highly on the application requirements. The following code comparison section provides additional architectural information that can help you in selecting the optimal microcontroller for your target embedded system