16 Chapter 2.Microcontroller Architectures C166,XE166 and XC2000 Architecture Advantages Extremely fast I/O operations via the Peripheral Event Controller High-speed interrupt system with very well-tuned peripherals Efficient arithmetic and fast memory access These devices are used in medium to large sized applications that require high I/O throughput.This architecture is well suited to the needs of embedded systems that involve a mixture of traditional controller code and DSP algorithms. ARM7 and ARM9 Architecture Advantages Huge linear address space The 16-bit Thumb instruction set provides high code density Efficient support for all C integer data types including pointer addressing ARM7 and ARM9-based microcontrollers are used for applications with large memory demands and for applications that use PC-based algorithms. Cortex-Mx Architecture Advantages One instruction set,Thumb2,reduces the complexity of the program code and eliminates the overhead needed for switching between ARM and Thumb instruction mode The Nested Vector Interrupt Controller(NVIC)removes interrupt prolog and epilog code,and provides several,configurable priority levels Extremely low power consumption with a variety of sleep modes The Cortex-Mx microcontroller architecture is designed for hard real-time systems,but can be used for complex System-on-Chip applications as well
16 Chapter 2. Microcontroller Architectures C166, XE166 and XC2000 Architecture Advantages Extremely fast I/O operations via the Peripheral Event Controller High-speed interrupt system with very well-tuned peripherals Efficient arithmetic and fast memory access These devices are used in medium to large sized applications that require high I/O throughput. This architecture is well suited to the needs of embedded systems that involve a mixture of traditional controller code and DSP algorithms. ARM7 and ARM9 Architecture Advantages Huge linear address space The 16-bit Thumb instruction set provides high code density Efficient support for all C integer data types including pointer addressing ARM7 and ARM9-based microcontrollers are used for applications with large memory demands and for applications that use PC-based algorithms. Cortex-Mx Architecture Advantages One instruction set, Thumb2, reduces the complexity of the program code and eliminates the overhead needed for switching between ARM and Thumb instruction mode The Nested Vector Interrupt Controller (NVIC) removes interrupt prolog and epilog code, and provides several, configurable priority levels Extremely low power consumption with a variety of sleep modes The Cortex-Mx microcontroller architecture is designed for hard real-time systems, but can be used for complex System-on-Chip applications as well
Getting Started:Creating Applications with uVision 17 Classic and Extended 8051 Devices 8051 devices combine cost-efficient hardware with a simple but efficient programming model that uses various memory regions to maximize code efficiency and speed-up memory access.The following figure shows the memory layout of a classic 8051 device 0x100 0xFFFF F8 98 CODE SFR 0x100 8051Bt SPACE 904 addressable 88k 0x0000 IDATA 256 Bytes 80k 0x80 0x80 2F 0xFFFF DATA 128 8051 DATA Bitspace 128 Bytes Bytes 20 XDATA 1 4 Register 0x0 Banks 6 0x0000 The 8051 architecture provides three different physical memory regions: DATA/IDATA memory includes a 256 Bytes on-chip RAM with register banks and bit-addressable space that is used for fast variable accessing. Some devices provide an extended data(EDATA)space with up to 64KB CODE memory consists of 64KB ROM space used for program code and constants.The Keil linker supports code banking that allows you to expand the physical memory space.In extended variants,up to 16MB ROM space is available. XDATA memory has a 64KB RAM space for off-chip peripheral and memory addressing.Today,most devices provide some on-chip RAM that is mapped into XDATA
Getting Started: Creating Applications with µVision 17 Classic and Extended 8051 Devices 8051 devices combine cost-efficient hardware with a simple but efficient programming model that uses various memory regions to maximize code efficiency and speed-up memory access. The following figure shows the memory layout of a classic 8051 device. The 8051 architecture provides three different physical memory regions: DATA/IDATA memory includes a 256 Bytes on-chip RAM with register banks and bit-addressable space that is used for fast variable accessing. Some devices provide an extended data (EDATA) space with up to 64KB. CODE memory consists of 64KB ROM space used for program code and constants. The Keil linker supports code banking that allows you to expand the physical memory space. In extended variants, up to 16MB ROM space is available. XDATA memory has a 64KB RAM space for off-chip peripheral and memory addressing. Today, most devices provide some on-chip RAM that is mapped into XDATA. CODE 0xFFFF 0x0000 0xFFFF 0x0000 DATA 128 Bytes 0x80 0x0 0x100 4 Register Banks 8051 Bitspace 0 20 DATA 128 Bytes 1F 88 0x80 F8 98 90 2F 80 SFR SPACE 0x100 8051 Bit addressable XDATA IDATA 256 Bytes
18 Chapter 2.Microcontroller Architectures SFR and IDATA memory are located in the same address space but are accessed through different assembler instructions For extended devices,the memory layout provides a universal memory map that includes all 8051-memory types in a single 16MByte address region 8051 Highlights Fast interrupt service routines with two or four priority levels and up to 32- vectored interrupts Four register banks for minimum interrupt prolog/epilog Bit-addressable space for efficient logical operations 128 Bytes of Special Function Register(SFR)space for tight integration of on-chip peripherals.Some devices extend the SFR space using paging. Low-power,high-speed devices up to 100 MIPS are available 8051 Development Tool Support The Keil C51 Compiler and the Keil Linker/Locator provide optimum 8051 architecture support with the following features and C language extensions. "Interrupt functions with register bank support are written directly in C Bit and bit-addressable variables for optimal Boolean data type support Compile-time stack with data overlaying uses direct memory access and gives high-speed code with little overhead compared to assembly programming Reentrant functions for usage by multiple interrupt or task threats "Generic and memory-specific pointers provide flexible memory access Linker Code Packing gives utmost code density by reusing identical program sequences Code and Variable Banking expand the physical memory address space Absolute Variable Locating enables peripheral access and memory sharing
18 Chapter 2. Microcontroller Architectures SFR and IDATA memory are located in the same address space but are accessed through different assembler instructions For extended devices, the memory layout provides a universal memory map that includes all 8051-memory types in a single 16MByte address region 8051 Highlights Fast interrupt service routines with two or four priority levels and up to 32- vectored interrupts Four register banks for minimum interrupt prolog/epilog Bit-addressable space for efficient logical operations 128 Bytes of Special Function Register (SFR) space for tight integration of on-chip peripherals. Some devices extend the SFR space using paging. Low-power, high-speed devices up to 100 MIPS are available 8051 Development Tool Support The Keil C51 Compiler and the Keil Linker/Locator provide optimum 8051 architecture support with the following features and C language extensions. Interrupt functions with register bank support are written directly in C Bit and bit-addressable variables for optimal Boolean data type support Compile-time stack with data overlaying uses direct memory access and gives high-speed code with little overhead compared to assembly programming Reentrant functions for usage by multiple interrupt or task threats Generic and memory-specific pointers provide flexible memory access Linker Code Packing gives utmost code density by reusing identical program sequences Code and Variable Banking expand the physical memory address space Absolute Variable Locating enables peripheral access and memory sharing
Getting Started:Creating Applications with uVision 19 8051 Memory Types A memory type prefix is used to assign a memory type to an expression with a constant.This is necessary,for example,when an expression is used as an address for the output command.Normally,symbolic names have an assigned memory type,so that the specification of the memory type can be omitted.The following memory types are defined: Prefix Memory Space C: Code Memory(CODE) D: Intemnal,direct-addressable RAM memory(DATA) 上 Internal,indirect-addressable RAM memory(IDATA) X: External RAM memory(XDATA) B: Bit-addressable RAM memory P: Peripheral memory (VTREGD-80x51 pins) The prefix P:is a special case,since it always must be followed by a name.The name in turn is searched for in a special symbol table that contains the register's pin names. Example: C:0x100 Address 0x100 in CODE memory ACC Address OxE0 in DATA memory,D: :100 Address 0x64 in internal RAM X:0FFFFH Address OxFFFF in external data memory B:0x7F Bit address 127 or 2FH.7 Q Address 0xD7(PSW.7),memory type B:
Getting Started: Creating Applications with µVision 19 8051 Memory Types A memory type prefix is used to assign a memory type to an expression with a constant. This is necessary, for example, when an expression is used as an address for the output command. Normally, symbolic names have an assigned memory type, so that the specification of the memory type can be omitted. The following memory types are defined: Prefix Memory Space C: Code Memory (CODE) D: Internal, direct-addressable RAM memory (DATA) I: Internal, indirect-addressable RAM memory (IDATA) X: External RAM memory (XDATA) B: Bit-addressable RAM memory P: Peripheral memory (VTREGD – 80x51 pins) The prefix P: is a special case, since it always must be followed by a name. The name in turn is searched for in a special symbol table that contains the register’s pin names. Example: C:0x100 Address 0x100 in CODE memory ACC Address 0xE0 in DATA memory, D: I:100 Address 0x64 in internal RAM X:0FFFFH Address 0xFFFF in external data memory B:0x7F Bit address 127 or 2FH.7 C Address 0xD7 (PSW.7), memory type B:
20 Chapter 2.Microcontroller Architectures Infineon C166,XE166,XC2000 The 16-bit architecture of these devices is designed for high-speed real-time applications.It provides up to 16MB memory space with fast memory areas mapped into parts of the address space.High-performance applications benefit from locating frequently used variables into the fast memory areas.The below listed memory types address the following memory regions: Memory Type Description bdata Bit-addressable part of the idata memory. huge Complete 16MB memory with fast 16-bit address calculation.Object size limited to 64KB. idata High speed RAM providing maximum access speed(part of sdata). near Efficient variable and constant addressing(max.64KB)with 16-bit pointer and 16-bit address calculation. sdata System area includes Peripheral Registers and additional on-chip RAM space. xhuge Complete 16MB memory with full address calculation for unlimited object size. C166,XE166,XC2000 Highlights Highest-speed interrupt handling with 16 priority levels and up to 128 vectored interrupts Unlimited register banks for minimum interrupt prolog/epilog Bit instructions and bit-addressable space for efficient logical operations ATOMIC instruction sequences are protected from interrupts without interrupt enable/disable sequences Peripheral Event Controller(PEC)for automatic memory transfers triggered by peripheral interrupts.Requires no processor interaction and further improves interrupt response time. Multiply-Accumulate Unit(MAC)provided for high-speed DSP algorithms
20 Chapter 2. Microcontroller Architectures Infineon C166, XE166, XC2000 The 16-bit architecture of these devices is designed for high-speed real-time applications. It provides up to 16MB memory space with fast memory areas mapped into parts of the address space. High-performance applications benefit from locating frequently used variables into the fast memory areas. The below listed memory types address the following memory regions: Memory Type Description bdata Bit-addressable part of the idata memory. huge Complete 16MB memory with fast 16-bit address calculation. Object size limited to 64KB. idata High speed RAM providing maximum access speed (part of sdata). near Efficient variable and constant addressing (max. 64KB) with 16-bit pointer and 16-bit address calculation. sdata System area includes Peripheral Registers and additional on-chip RAM space. xhuge Complete 16MB memory with full address calculation for unlimited object size. C166, XE166, XC2000 Highlights Highest-speed interrupt handling with 16 priority levels and up to 128 vectored interrupts Unlimited register banks for minimum interrupt prolog/epilog Bit instructions and bit-addressable space for efficient logical operations ATOMIC instruction sequences are protected from interrupts without interrupt enable/disable sequences Peripheral Event Controller (PEC) for automatic memory transfers triggered by peripheral interrupts. Requires no processor interaction and further improves interrupt response time. Multiply-Accumulate Unit (MAC) provided for high-speed DSP algorithms