ISA-based data acquisition and control board The hardware is a PC-based data acquisition and control board with many capabilities. It can accept up to 8 analog inputs, produce 2 analog outputs, accept up to 67 digital(switch) inputs and produce 8 digital outputs. It also offers the opportunity for expansion by provid ing buffered ddress, data and select lines. In addition, a spare AND gate and two spare NOR gates are made available, along with a small bread board ing area feEt LLULELL INPUT ::2:: TREBLE 品=出 品名3 VOLUME 品tt SPEAKER THE CIRCUIT You will see references to PdF data sheets in the following descriptions. The data sheets might show parts with variations on the part number, but they will have the same functionality This section will cover parts of the circuit not covered in the experiments Port addresses on a typical PC Industry Standard Architecture (ISa)bus are derived from the ten address lines AO through A9, with A9 always high. Note that all buffered lines in the schematics are prefixed with the letter B. Half of IC7, a 74LS244 buffer, is used to buffer the first three nd dress lines and the reset line Base address selection is made by three dip switch sections connected to ICll, a 74LS6888-bit magnitude comparator
ISA-based data acquisition and control board The hardware is a PC-based data acquisition and control board with many capabilities. It can accept up to 8 analog inputs, produce 2 analog outputs, accept up to 67 digital (switch) inputs and produce 8 digital outputs. It also offers the opportunity for expansion by providing buffered address, data and select lines. In addition, a spare AND gate and two spare NOR gates are made available, along with a small breadboarding area. THE CIRCUIT You will see references to PDF data sheets in the following descriptions. The data sheets might show parts with variations on the part number, but they will have the same functionality. This section will cover parts of the circuit not covered in the experiments. Port addresses on a typical PC Industry Standard Architecture (ISA) bus are derived from the ten address lines A0 through A9, with A9 always high. Note that all buffered lines in the schematics are prefixed with the letter B. Half of IC7, a 74LS244 buffer, is used to buffer the first three address lines and the RESET line. Base address selection is made by three DIP switch sections connected to IC11, a 74LS688 8-bit magnitude comparator:
Pin 19 NXOR Gates Inverters Pin 1 The main logic elements in the 74LS688 are the NXOr gates Recall from the boolean Logic section that an XOR gate will produce a high output if the inputs are different The NOR does the same thing but inverts the output. The output of one of the nOR gates above will be low if its outputs are different. If its inputs are the same, its output will be high. Although pairs of inputs go through inverting buffers, the logic is not changed. When all of the NXOR outputs go high along with the enable input on pin 1, the 9-input NAND gate output will go low When a switch is closed, its input to the 74LS688 is taken low. When the switch is open, the input is pulled up by a resistor in an array. Corresponding inputs to the comparator are connected to address lines A6 through A8. If a switch is open, its corresponding address line must be high to make the output of its NXOR high. If a switch is closed, its corresponding address line must be low. A9 is also connected, with its correspond ing input taken high. Similarly, the AEN (address enable) line is connected to the comparator with its corresponding input connected to ground. AEN is low with a valid port address. The three other pairs are taken high. Finally, either the I/O Read (IOR)or the I/O Write(loW)line must be low for there to be a valid port address The bars over IOR and iow in the schematic mean they are active low. IOR and low are first buffered by using two And gates with one side tied high in IC8, a 74LSO8, then ANDed using a third. The result is a signal that will go low if either IOW or IOR goes low. This is tied to the pin enable input of the 74LS688. When all conditions are satisfied, pin 19 of the 74LS688 will go lo Following are the heX addresses that can be selected by setting the Dip switches on(1)and off (0), and the possible conflicts that might arise(means"through") WITCH 23 ADDRESS POSSIBLE CONFLICTS 11 2oo-23F 200-20F=game port 011 P40-27F 278-27F=LPT2(OK with no spares used -see below) l01 280- 2BF 2B0-2DF= Alternate EGA 01 2C0 -2FF 2B0-2DF= Alternate EGA 300-33F 00-31F=Some Sound Cards and The Prototype Card 10 340-37F 378-37F=LPTI(OK with no spares used)
The main logic elements in the 74LS688 are the NXOR gates. Recall from the Boolean Logic section that an XOR gate will produce a high output if the inputs are different. The NXOR does the same thing but inverts the output. The output of one of the NXOR gates above will be low if its outputs are different. If its inputs are the same, its output will be high. Although pairs of inputs go through inverting buffers, the logic is not changed. When all of the NXOR outputs go high along with the enable input on pin 1, the 9-input NAND gate output will go low. When a switch is closed, its input to the 74LS688 is taken low. When the switch is open, the input is pulled up by a resistor in an array. Corresponding inputs to the comparator are connected to address lines A6 through A8. If a switch is open, its corresponding address line must be high to make the output of its NXOR high. If a switch is closed, its corresponding address line must be low. A9 is also connected, with its corresponding input taken high. Similarly, the AEN (address enable) line is connected to the comparator with its corresponding input connected to ground. AEN is low with a valid port address. The three other pairs are taken high. Finally, either the I/O Read (IOR) or the I/O Write (IOW) line must be low for there to be a valid port address. The bars over IOR and IOW in the schematic mean they are active low. IOR and IOW are first buffered by using two AND gates with one side tied high in IC8, a 74LS08, then ANDed using a third. The result is a signal that will go low if either IOW or IOR goes low. This is tied to the pin 1 enable input of the 74LS688. When all conditions are satisfied, pin 19 of the 74LS688 will go low. Following are the HEX addresses that can be selected by setting the DIP switches on (1) and off (0), and the possible conflicts that might arise (~ means "through"): SWITCH 1 2 3 ADDRESS POSSIBLE CONFLICTS 1 1 1 200 ~ 23F 200 ~ 20F = game port 0 1 1 240 ~ 27F 278 ~ 27F = LPT2 (OK with no spares used -- see below) 1 0 1 280 ~ 2BF 2B0 ~ 2DF = Alternate EGA 0 0 1 2C0 ~ 2FF 2B0 ~ 2DF = Alternate EGA 1 1 0 300 ~ 33F 300 ~ 31F = Some Sound Cards and The Prototype Card 0 1 0 340 ~ 37F 378 ~ 37F = LPT1 (OK with no spares used)
00 380-3BF 380- 38F= bisynchronous 2 390-393=cluster BAO-3AF =bisynchronous 1 3B0-3BF =mono adapter and printer adapte 000 3C0-3FF BC0- 3CF=EGA The best choices would probably be HEX 200 or 300. If the board is used on a dedicated computer however, any conflicting devices not used could be removed from the computer IC12, a 74LS138 3-to-8 line decoder/multiplexer, uses address lines A3 through A5 to break the above up into eight byte chunks used by devices on the board. The device selections for all possible switch settings are shown below. The first entry for each corresponds to the base ddress in the table above. Don't be concerned if you don 't know what some of the items in the tables mean. They will be covered in the experiments 207 Eight Channel Analog to Digital Converter P08-20F Digital to Analog Converter 1 210-217 Digital to Analog Converter 2(optional) P18-2IF Analog to Digital Converter Ready Line And 3 Digital Inputs 20-227 Programmable Peripheral Interface P28-22F Spare Select Line P30-237 Spare Select Line P38-23F Spare Select Line P40-247 Eight Channel Analog to Digital Converter P48-24F Digital to Analog Converter 1 250-257 Digital to Analog Converter 2(optional) P58-25F Analog to Digital Converter Ready Line And 3 Digital Inputs 60-267 Programmable Peripheral Interface P68-26F Spare Select Line P70-277 Spare Select Line 278-27F spare Select Line
1 0 0 380 ~ 3BF 380 ~ 38F = bisynchronous 2 390 ~ 393 = cluster 3A0 ~ 3AF = bisynchronous 1 3B0 ~ 3BF = mono adapter and printer adapter 0 0 0 3C0 ~ 3FF 3C0 ~ 3CF = EGA The best choices would probably be HEX 200 or 300. If the board is used on a dedicated computer however, any conflicting devices not used could be removed from the computer. IC12, a 74LS138 3-to-8 line decoder/multiplexer, uses address lines A3 through A5 to break the above up into eight byte chunks used by devices on the board. The device selections for all possible switch settings are shown below. The first entry for each corresponds to the base address in the table above. Don't be concerned if you don't know what some of the items in the tables mean. They will be covered in the experiments. 200 ~ 207 Eight Channel Analog to Digital Converter 208 ~ 20F Digital to Analog Converter 1 210 ~ 217 Digital to Analog Converter 2 (optional) 218 ~ 21F Analog to Digital Converter Ready Line And 3 Digital Inputs 220 ~ 227 Programmable Peripheral Interface 228 ~ 22F Spare Select Line 230 ~ 237 Spare Select Line 238 ~ 23F Spare Select Line 240 ~ 247 Eight Channel Analog to Digital Converter 248 ~ 24F Digital to Analog Converter 1 250 ~ 257 Digital to Analog Converter 2 (optional) 258 ~ 25F Analog to Digital Converter Ready Line And 3 Digital Inputs 260 ~ 267 Programmable Peripheral Interface 268 ~ 26F Spare Select Line 270 ~ 277 Spare Select Line 278 ~ 27F Spare Select Line
P80-287 Eight Channel Analog to Digital Converter 288-28F Digital to Analog Converter 1 297 Digital to Analog Converter 2(optional) P98-29F Analog to Digital Converter Ready Line And 3 Digital Inputs PAO-2A7 Programmable Peripheral Interface PA8-2AF Spare Select Line PBO-2B7 Spare Select Line PB8- 2BF Spare Select Line PCo-2C7 Eight Channel Analog to Digital Converter kC8-2CF Digital to Analog Converter 1 RDo-2D7 Digital to Analog Converter 2(optional) PD8-2DF Analog to Digital Converter Ready Line and 3 Digital Inputs PEO-2E7 Programmable Peripheral Interface PE8-2EF Spare Select Line PFO-2F7 Spare Select Line PF8-2FF spare Select Line 300-307 Eight Channel Analog to Digital Converter B08-30F Digital to Analog Converter 1 0-317 Digital to Analog Converter 2(optional) B18-3IF Analog to Digital Converter Ready Line And 3 Digital Inputs 320-327 Programmable Peripheral Interface 28-32F Spare Select Line 330-337 Spare Select Line 38-33F spare Select Line
280 ~ 287 Eight Channel Analog to Digital Converter 288 ~ 28F Digital to Analog Converter 1 290 ~ 297 Digital to Analog Converter 2 (optional) 298 ~ 29F Analog to Digital Converter Ready Line And 3 Digital Inputs 2A0 ~ 2A7 Programmable Peripheral Interface 2A8 ~ 2AF Spare Select Line 2B0 ~ 2B7 Spare Select Line 2B8 ~ 2BF Spare Select Line 2C0 ~ 2C7 Eight Channel Analog to Digital Converter 2C8 ~ 2CF Digital to Analog Converter 1 2D0 ~ 2D7 Digital to Analog Converter 2 (optional) 2D8 ~ 2DF Analog to Digital Converter Ready Line And 3 Digital Inputs 2E0 ~ 2E7 Programmable Peripheral Interface 2E8 ~ 2EF Spare Select Line 2F0 ~ 2F7 Spare Select Line 2F8 ~ 2FF Spare Select Line 300 ~ 307 Eight Channel Analog to Digital Converter 308 ~ 30F Digital to Analog Converter 1 310 ~ 317 Digital to Analog Converter 2 (optional) 318 ~ 31F Analog to Digital Converter Ready Line And 3 Digital Inputs 320 ~ 327 Programmable Peripheral Interface 328 ~ 32F Spare Select Line 330 ~ 337 Spare Select Line 338 ~ 33F Spare Select Line
340-347 Eight Channel Analog to Digital Converter 348-34F Digital to Analog Converter 1 357 Digital to Analog Converter 2(optional) 358-35F Analog to Digital Converter Ready Line And 3 Digital Inputs 360-367 Programmable Peripheral Interface 368-36F Spare Select Line B70-377 Spare Select Line B78-37F Spare Select Line 380-387 Eight Channel Analog to Digital Converter B88-38F Digital to Analog Converter 1 990-397 Digital to Analog Converter 2(optional) B98-39F Analog to Digital Converter Ready Line And 3 Digital Inputs BA0-3A7 Programmable Peripheral Interface A8-3AF Spare Select Line BBO-3B7 Spare Select Line BB8-3BF spare Select Line 3Co-3C7 Eight Channel Analog to Digital Converter BC8-3CF Digital to Analog Converter 1 BD0-3D7 Digital to Analog Converter 2(optional) BD8-3DF Analog to Digital Converter Ready Line And 3 Digital Inputs BE0-3E7 Programmable Peripheral Interface E8-3EF Spare Select Line BFO-3F7 Spare Select Line BF8-3FF spare Select Line
340 ~ 347 Eight Channel Analog to Digital Converter 348 ~ 34F Digital to Analog Converter 1 350 ~ 357 Digital to Analog Converter 2 (optional) 358 ~ 35F Analog to Digital Converter Ready Line And 3 Digital Inputs 360 ~ 367 Programmable Peripheral Interface 368 ~ 36F Spare Select Line 370 ~ 377 Spare Select Line 378 ~ 37F Spare Select Line 380 ~ 387 Eight Channel Analog to Digital Converter 388 ~ 38F Digital to Analog Converter 1 390 ~ 397 Digital to Analog Converter 2 (optional) 398 ~ 39F Analog to Digital Converter Ready Line And 3 Digital Inputs 3A0 ~ 3A7 Programmable Peripheral Interface 3A8 ~ 3AF Spare Select Line 3B0 ~ 3B7 Spare Select Line 3B8 ~ 3BF Spare Select Line 3C0 ~ 3C7 Eight Channel Analog to Digital Converter 3C8 ~ 3CF Digital to Analog Converter 1 3D0 ~ 3D7 Digital to Analog Converter 2 (optional) 3D8 ~ 3DF Analog to Digital Converter Ready Line And 3 Digital Inputs 3E0 ~ 3E7 Programmable Peripheral Interface 3E8 ~ 3EF Spare Select Line 3F0 ~ 3F7 Spare Select Line 3F8 ~ 3FF Spare Select Line