TABLE 4.1: Can both r1 and r2 be Sct to O? Core cl Core c2 Comments SI: x= NEW: S2: y=NEW: /* Initially,x=0&y=0*/ LI: rl=y L2:2=x S2: y= NEW: P NEW" L2:r2=X/0 SI:X=NEW: F NEW #/ rl=y: / NE Outcome:(rl, r2)=(NEW. 0) (c)TSo SC Execution 3 SI: X= NEW:/ NEW 5 S2:y=NEW;/NEW考 L:rl=y;/*0制 L2:n2=x/0” Outcome: (rl, r2)=(0, 0) (d) TSO Execution, but NOT an SC Execution RE 4.2: Four alternative tso Executions of table 4.I's program 2021/2/11 计算机体系结构
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TABLE 4.3: Can rl or r3 be set to 0> Core C1 Core C2 Comments SI: X=NEW: NEW /* Initially. x=0&y=0*/ LI: rI=x: L3:r3=y; L2:r2=y; L4:r4=x; / Assume r2=0&r4=0*/ 当(r2,r4)=(0,0)时,(r1,r3)一定为(0,0)? 2021/2/11 计算机体系结构 13
• 当(r2, r4) = (0, 0) 时，（r1, r3) 一定为 (0, 0）？ 2021/2/11 计算机体系结构 13
program order(<p) of Core CI memory order(<n program order(<p)of Core C2 SI: X=NEW: /NEW*/ S2: y=NEW: /NEW/ LI: rl=x: NEW s bypass bypass L3: r3=y: NEW 3/ L2:r2=y;/*0* L4:r4=x;/0* Outcome:(r2, r4)=(0, 0) and (rl, r3)=(NEW, NEW) FIGURE 4.3: A TSO Execution of Table 4-3's Program(with"bypassing") 2/112021 中国科学技术大学
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Memory Fences Instructions to sequentialize memory accesses 实现弱同一性或放松的存储器模型的处理器(允许针对不同地址的 loads和 stores操作乱序)需要提供存储器栅栏指令来强制对某些存储 器操作串行化 Examples of processors with relaxed memory models: Sparc V8 (TSO, PSO): Membar Sparc v9(rMo): Membar #loadload membar #load store Membar storeload membar store store PowerPC(WO): SynC, CIElo ARM: DMB (Data Memory Barrier) X86/ 64: mfence(Global Memory Barrier) 存储器栅栏是一种代价比较大的操作,仅仅在需要时,对存器架作 行化 2021/2/11 计算机体系结构 15
Memory Fences Instructions to sequentialize memory accesses 15 实现弱同一性或放松的存储器模型的处理器（允许针对不同地址的 loads 和stores操作乱序）需要提供存储器栅栏指令来强制对某些存储 器操作串行化 Examples of processors with relaxed memory models: Sparc V8 (TSO,PSO): Membar Sparc V9 (RMO): Membar #LoadLoad, Membar #LoadStore Membar #StoreLoad, Membar #StoreStore PowerPC (WO): Sync, EIEIO ARM: DMB (Data Memory Barrier) X86/64: mfence (Global Memory Barrier) 存储器栅栏是一种代价比较大的操作，仅仅在需要时，对存储器操作串 行化 2021/2/11 计算机体系结构
Table 1. s ofm Q3s 333 8-3多 品≌艺2∈≌E 三 8器 房房 Alpha AMD64 A64 (PA-RISC) PA-RISC CPUS POWER (SPARC so￥ SPARC 0) SPARC TSO x86 (x86 OOStore 2021/2/11 计算机体系结构
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