Tag array Data array Way.Way N-1 Wa0|…WayN1 Tags i 与 way1 index offset Aligner Address Hit Miss Data IGURE 2.1: High-level logical cache organization 2021/2/4 计算机体系结构
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Address calculation disambiguation C ache access Result Data Array Address Tag calculation 6号 Array FIGURE 2.2: Parallel tag and data array access pipeline 2021/2/4 计算机体系结构
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Wayo L ag array Way0…WayN1 Set i index offset Aligner 7 addre HitLess FIG URE 2.3: High -level logical cache organization with serial tag and data array access 2021/2/4 计算机体系结构
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Address calcul ati on Disambiguation Tag access Data access Result drive Data Address 别￥g Tag 2 calculation Array FIGURE 2.4: Serial tag and data array access pipeline. 2021/2/4 计算机体系结构
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直接映像 Cache查找过程 Data-in byte offset word select + Aligner write b Tag 0 Data block o k Tag 1 Data block 1 oom ag 2k-1 Block2*-1 enable Aligner byte offset Data-out Enable write access to Aligner shifts data within data block if cache hit word according to byte offset 2021/2/4 计算机体系结构
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