Daya BayReadout board diagram113TDCalgorithm: Gray countersOn board calibrationcircuitHihsDAX16Single channel macro in FPGAStatus bits 2 triggertimeTDCOver thresholdstartthresholdTestinpToVMEbusDATADLLDACBUFFERFromPMT80 MHz ClockdividerVME40MHzinterfaceHinhspeedshapingchargePealAD9244Hit number or trigger pattemFindingto triggermotFPGAEVDSX6RC=300ns14bit/40MSPSDAOFlash ADCCH116ChannelinputsCH2CH3fast Q sum to triggTrigger AigorithmCH4ndedtoDaughterCarddiftfastQsumtoFADCboardSingleCH13CH14CH15CH1667th高能物理学会大会，李小男，高能物理研究所
7 th 高能物理学会大会, 李小男, 高能物理研究所 6 Readout board diagram From PMT -5V 50 High speed Amp AD8021 AD9244 14bit/40MSPS Flash ADC FPGA To VME bus CH1 Single ended to diff. fast Q sum to trigger shaping threshold start stop CH2 Disc. L1 TDC Peak Finding 40MHz charge time DATA BUFFER L1 VME interface Single channel macro in FPGA X 16 RC=300ns Test input Over threshold Hit number or trigger pattern to trigger module X 2 K CH3 CH4 CH13 CH14 CH15 CH16 SUM DAC DAC LVDS x 6 RC2 High speed DAC Status bits 2 trigger DLL 80 MHz Clock Single ended to diff. fast Q sum to FADC board divider Trigger Algorithm Daughter Card On board calibration circuit 16 Channel inputs TDC algorithm: Gray counters
Daya BayTrigger requirement13Good backgroundrejectionpowerratecangoto~KHzratelimitedbyDAQcapabilities(hopefully<10MB/s/module)Lowthreshold(T+3o<1MeV)Record prompt positron signals and delayed signals from the neutrinointeractions.RecordthebackgroundtoenablebackgroundanalysisHighandwellknownefficiencyFlexibility(tofight backgrounds), same trigger boardfor differentdetector.FPGADaughtercardReliability(toreducesystematicerrors)Independency,Separatetriggerforeach of neutrino module,andeachof muon detector,water pool,watercenrenkovmodule andRPC.Redundancy(to measurethe triggerefficiency)Providea systemclock7th高能物理学会大会，李小男，高能物理研究所1
7 th 高能物理学会大会, 李小男, 高能物理研究所 7 Trigger requirement • Good background rejection power rate can go to ~KHz rate limited by DAQ capabilities (hopefully < 10 MB/s/module) • Low threshold ( T+3s < 1MeV ) – Record prompt positron signals and delayed signals from the neutrino interactions. – Record the background to enable background analysis. • High and well known efficiency • Flexibility (to fight backgrounds), same trigger board for different detector. – FPGA – Daughter card • Reliability (to reduce systematic errors) • Independency, Separate trigger for each of neutrino module, and each of muon detector, water pool, water cenrenkov module and RPC. • Redundancy (to measure the trigger efficiency) • Provide a system clock