Address translation for Hierarchical page table The root page always remains In main memory Virtual Address I 10 bits 10 bits12bits Frame#Offset table Page Root page table (contains 102 PTEs) 102 PTESI Program Paging mechanism Main Memory 16 Figure 8.5 Address Translation in a Two-Level Paging System
16 Address Translation for Hierarchical page table The root page always remains in main memory
Translation lookaside Buffer Each virtual memory reference can cause two physical memory accesses One to fetch the page table One to fetch the data To overcome this problem a high-speed cache is set up for page table entries Called a Translation Lookaside Buffer tlB) Contains page table entries that have been most recently used
17 Translation Lookaside Buffer • Each virtual memory reference can cause two physical memory accesses – One to fetch the page table – One to fetch the data • To overcome this problem a high-speed cache is set up for page table entries – Called a Translation Lookaside Buffer (TLB) – Contains page table entries that have been most recently used