library ieee use ieee std_logic_1164. all; entity nand_3is port(a, b, c: in std_logic, y: out std_logic end nand 3 architecture one of nand 3 is b egin y<=not(a and b and c; end one;
library ieee; use ieee.std_logic_1164.all; entity nand_3 is port(a,b,c:in std_logic; y: out std_logic); end nand_3; architecture one of nand_3 is begin y<=not (a and b and c); end one;
采用进程语句结构 libraryieee; 信号 use ieee std_logic_1164. all entity nand 3is port(a, b, c: in std_logic; y: out std_logic) end nand 3 architecture one of nand 3is signal abc: std _logic_vector(2 downto0);--结构体说明语句 abc<=a&b&zc;--进程语句说明 process(abc)is begin case abc is when“000”=>y<=1 when“001″=>y< y When“010”=>y<=‘1’; when“011=>y<=1′; when“100 >y< when“101”=>y<=(1’; when“110″=>y<= when“1111y<=“0; when others=>null: end case, end process; end one?
采用进程语句结构 ——信号 library ieee; use ieee.std_logic_1164.all; entity nand_3 is port(a,b,c:in std_logic; y: out std_logic); end nand_3; architecture one of nand_3 is signal abc: std_logic_vector (2 downto 0); --结构体说明语句 begin abc<=a & b & c; --进程语句说明 process(abc) is begin case abc is when “000” => y<=‘1’; when “001” => y<=‘1’; when “010” => y<=‘1’; when “011” => y<=‘1’; when “100” => y<=‘1’; when “101” => y<=‘1’; when “110” => y<=‘1’; when “111” => y<=‘0’; when others =>null; end case; end process; end one;