How many time spend on each Module Compilation Times Compiler Netlist Extractor 90:99:04 Database builder 90:86:4 Logic Synthesize 00:6:18 Most of the time spend on Partitioner 90:6:5 thiS TWo modules Fitter 60: 60:18 Timing SNF Extractor 90:08:02 Assembler 0:98:2 Total time 00:06:37 Shange mths Copyright 1997 Altera Corporation 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.6 How many time spend on each Module Most of the time spend on this TWO MODULES
What you can do for Netlist/database Part Compiler Database Smart/Total Compiler can help Netlist Builder Smart Compiler Extractor if this is first time compilation save the database result for future compilation Processing Interfaces Assign Options Design Doctor if this is second compilation without modify of Design Doctor Settings the design, this step will be skipped Functional SNF Extractor Total compiler y Timing SNF Extract Optimize Timing SNIF no matter the design has been modified or not ed SNF Extractor the system will go through this step again Fitter Settings Report File Settings Turn on Smart Compiler Generate AHDL TDO File first time need longer than Total Compiler need more harddisk space to store the database Total recompile nformation Preserve All Node Name Synonyms subsequence will need LESS TIME than Total Compiler Copyright 1997 Altera Corporation 2/22/2021P7 favara
Copyright © 1997 Altera Corporation 2/22/2021 P.7 What you can do for Netlist/Database Part ◼ Smart/Total Compiler can help – Smart Compiler • if this is first time compilation, save the database result for future compilation • if this is second compilation without modify of the design, this step will be skipped – Total Compiler • no matter the design has been modified or not, the system will go through this step again ◼ Turn on Smart Compiler – first time need longer than Total Compiler – need more harddisk space to store the database information – subsequence will need LESS TIME than Total Compiler
What you can do for Logic Synthesiser Part Logic a Only turn on the option which is ueeful Synthesizer turn on XOR Synthesis under FE, useless turn on Parallel Expanders t fLEX is useless Project Name ir: Untitedl. di a If you design file is EDIRM)ich is already lobal Project Synthesis Style 1 oPtimize WYSIWYG Optimize by Synopsys) you can min tit. pend on the Max+ Plus ll Logic MAX Device Synthesis Options Synthesize O Mult- Level Synthesis for HAX 5000/7000 Devices s eithe WYSIWYG rOne-Hot Stale Machine Encoding don't forget to turn on Cascade/Carry 「 Automatic Register Packing Chain for flex device AUtomatic Open-Drain Pir T Automatic Implement in EAB don't forget to turn on the Parallel Expanders for MAX device you can also let Max+ Plus l does further Logic ptimize for you /AbsRA 2/22/2021P favara
Copyright © 1997 Altera Corporation 2/22/2021 P.8 What you can do for Logic Synthesiser Part ◼ Only turn on the Option which is useful – turn on XOR Synthesis under FLEX is useless – turn on Parallel Expanders under FLEX is useless ◼ If you design file is EDIF which is already Optimize by Synopsys – you can min. time spend on the Max+Plus II Logic Synthesizer • Select the WYSIWYG – don’t forget to turn on Cascade/Carry Chain for FLEX device – don’t forget to turn on the Parallel Expanders for MAX device – you can also let Max+Plus II does further Logic Optimize for you