Machine Language Consider the load-word and store-word instructions What would the regularity principle have us do? New principle: Good design demands a compromise Introduce a new type of instruction format I-type for data transfer instructions other format was R-type for register Example: lw $to, 32 ($s 2 35189 32 op rs rt 16 bit number Where's the compromise? 北京大学计算机科学技术系 计算机系统结枃教硏室
GÜWÑÇj°_+ ÑÇj+´DÔ e&RQVLGHUWKHORDGZRUGDQGVWRUHZRUGLQVWUXFWLRQV :KDWZRXOGWKHUHJXODULW\SULQFLSOHKDYHXVGR" 1HZSULQFLSOH *RRGGHVLJQGHPDQGVDFRPSURPLVH e,QWURGXFHDQHZW\SHRILQVWUXFWLRQIRUPDW ,W\SHIRUGDWDWUDQVIHULQVWUXFWLRQV RWKHUIRUPDWZDV5W\SHIRUUHJLVWHU e([DPSOH OZ W V RS UV UW ELWQXPEHU :KHUH VWKHFRPSURPLVH" 0DFKLQH/DQJXDJH
Stored Program Concept ° nstructions are bits Programs are stored in memory to be read or written just like data memory for data, programs, compilers, editors, etc. Processor Memory K ° Fetch& Execute Cycle Instructions are fetched and put into a special register Bits in the register"control"the subsequent actions Fetch the next instruction and continue 北京大学计算机科学技术系 计算机系统结枃教硏室
GÜWÑÇj°_+ ÑÇj+´DÔ e,QVWUXFWLRQV DUHELWV e3URJUDPVDUHVWRUHGLQPHPRU\WREHUHDGRUZULWWHQMXVWOLNHGDWD e)HWFK ([HFXWH&\FOH ,QVWUXFWLRQVDUHIHWFKHGDQGSXWLQWRDVSHFLDOUHJLVWHU %LWVLQWKHUHJLVWHUFRQWUROWKHVXEVHTXHQWDFWLRQV )HWFKWKHQH[WLQVWUXFWLRQDQGFRQWLQXH 3URFHVVRU 0HPRU\ PHPRU\IRUGDWDSURJUDPV FRPSLOHUVHGLWRUVHWF 6WRUHG3URJUDP&RQFHSW
Control Decision making instructions alter the control flow, i.e.. change the "next instruction to be executed MIPS conditional branch instructions bne sto, st1, Label beq $to, $tl, Label ° Example:i(i=j)h=i+ bne sso, Ss1, Label add ss3, Ss0, $s1 Label 北京大学计算机科学技术系 计算机系统结枃教硏室
GÜWÑÇj°_+ ÑÇj+´DÔ e'HFLVLRQPDNLQJLQVWUXFWLRQV DOWHUWKHFRQWUROIORZ LHFKDQJHWKHQH[WLQVWUXFWLRQWREHH[HFXWHG e0,36FRQGLWLRQDOEUDQFKLQVWUXFWLRQV EQH WW /DEHO EHT WW /DEHO e([DPSOH LI L M K LM EQH VV /DEHO DGGV VV /DEHO &RQWURO
Control MIPS unconditional branch instructions 3 label ° Example if (i!=j) beq ss4, $s5, Lab1 h=1t] add ss3, Ss4 Ss5 else 3 Lab2 h=i-ii Labl: sub $s3, $s4, $s5 Lab2 Can you build a sample for loop 北京大学计算机科学技术系 计算机系统结枃教硏室
GÜWÑÇj°_+ ÑÇj+´DÔ e0,36XQFRQGLWLRQDOEUDQFKLQVWUXFWLRQV M ODEHO e([DPSOH LI L M EHT VV /DE K LM DGGV VV HOVH M/DE K LM /DE VXEV VV /DE e&DQ\RXEXLOGD VDPSOHIRUORRS" &RQWURO
So far ° nstruction Meaning add ssl, $s2, $s3 Ss1 =$s2 ss3 sub ssl, Ss2 Ss3 Ss1 =$$s3 1wSs1,100(Ss2) ssl Memory [$s2+100 sw $s1, 100($s2 Memory [$s2+100]=$s1 bne Ss4, $s5,I Next instr. is at label if ss4 $s5 beq $s4, $s5, I Next instr. is at Label if ss4 = ss5 3 Label Next instr. is at label ° Formats ES rt ra shamt funct R工J Es rt 16 bit address 26 bit address 北京大学计算机科学技术系 计算机系统结枃教硏室
GÜWÑÇj°_+ ÑÇj+´DÔ 6RIDU e,QVWUXFWLRQ 0HDQLQJ DGGVVV V VV VXEVVV V V V OZ V V V 0HPRU\>V@ VZ V V 0HPRU\>V@ V EQH VV/ 1H[W LQVWULVDW/DEHOLIV≠ V EHT VV/ 1H[W LQVWULVDW/DEHOLIV V M/DEHO 1H[WLQVWULVDW/DEHO e)RUPDWV RS UV UW UG VKDPW IXQFW RS UV UW ELWDGGUHVV RS ELWDGGUHVV 5 , -