R-S NAND Latch By definition, Q can never be equal to Q because one is the inverse of the other when Rs=oo, the circuit will cause Q=Q.It creates an undefined condition for q and Q output a Therefore the case when rs=00 is illegal and not allow for the nand latch
•R-S NAND Latch ◼ By definition, Q can never be equal to Q’ because one is the inverse of the other. ◼ when RS=00, the circuit will cause Q=Q’. It creates an undefined condition for Q and Q’ output. ◼ Therefore, the case when RS=00 is illegal and not allow for the NAND latch
R=1.S=1 T G1G2 G1 G2 R Output next state 2=00=1
0 0 R=0, S=0 1 1 R=1, S=1 1 1 1 1 0 0 R S Q’ Q G1 G2 TG1>TG2 Output next state Q = 0 Q'= 1 1
R=1.S=1 TGLTG2 G1 G2 R 0S Output next state 0=1 Q=0
0 0 R=0, S=0 1 1 R=1, S=1 1 1 1 1 0 R 0 S Q’ Q G1 G2 TG1<TG2 Output next state Q = 1 Q'= 0 1
R=1.S=1 TGI=Tg2 G1 G2 R No stable output, oscillate
0 0 R=0, S=0 1 1 R=1, S=1 1 1 1 1 0 0 R S Q’ Q G1 G2 TG1=TG2 No stable output , Oscillate 0 0 1 1 1 1 0 0 0 0
Rs nor latch ■ Analysis 口R=0,5=0Ql=Q Qn+1=Q 口R=1,S=0Qm=0 R Q+1=1 口R=0,5=1Q1=1 Qm1=0 口R=1,S=1Qm1=O Qm+1=0 R
• R -S NOR Latch ◼ Analysis R=0, S=0 Qn+1=Q; Qn+1’=Q’; R=1, S=0 Qn+1=0; Qn+1’=1; R=0, S=1 Qn+1=1; Qn+1’=0; R=1, S=1 Qn+1=0; Qn+1’=0; S R Q’ Q SR Q’ Q